1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/mediatek-dwmac.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MediaTek DWMAC glue layer controller
8
9maintainers:
10  - Biao Huang <biao.huang@mediatek.com>
11
12description:
13  This file documents platform glue layer for stmmac.
14
15# We need a select here so we don't match all nodes with 'snps,dwmac'
16select:
17  properties:
18    compatible:
19      contains:
20        enum:
21          - mediatek,mt2712-gmac
22          - mediatek,mt8195-gmac
23  required:
24    - compatible
25
26allOf:
27  - $ref: "snps,dwmac.yaml#"
28
29properties:
30  compatible:
31    oneOf:
32      - items:
33          - enum:
34              - mediatek,mt2712-gmac
35          - const: snps,dwmac-4.20a
36      - items:
37          - enum:
38              - mediatek,mt8195-gmac
39          - const: snps,dwmac-5.10a
40
41  clocks:
42    minItems: 5
43    items:
44      - description: AXI clock
45      - description: APB clock
46      - description: MAC Main clock
47      - description: PTP clock
48      - description: RMII reference clock provided by MAC
49      - description: MAC clock gate
50
51  clock-names:
52    minItems: 5
53    items:
54      - const: axi
55      - const: apb
56      - const: mac_main
57      - const: ptp_ref
58      - const: rmii_internal
59      - const: mac_cg
60
61  mediatek,pericfg:
62    $ref: /schemas/types.yaml#/definitions/phandle
63    description:
64      The phandle to the syscon node that control ethernet
65      interface and timing delay.
66
67  mediatek,tx-delay-ps:
68    description:
69      The internal TX clock delay (provided by this driver) in nanoseconds.
70      For MT2712 RGMII interface, Allowed value need to be a multiple of 170,
71      or will round down. Range 0~31*170.
72      For MT2712 RMII/MII interface, Allowed value need to be a multiple of 550,
73      or will round down. Range 0~31*550.
74      For MT8195 RGMII/RMII/MII interface, Allowed value need to be a multiple of 290,
75      or will round down. Range 0~31*290.
76
77  mediatek,rx-delay-ps:
78    description:
79      The internal RX clock delay (provided by this driver) in nanoseconds.
80      For MT2712 RGMII interface, Allowed value need to be a multiple of 170,
81      or will round down. Range 0~31*170.
82      For MT2712 RMII/MII interface, Allowed value need to be a multiple of 550,
83      or will round down. Range 0~31*550.
84      For MT8195 RGMII/RMII/MII interface, Allowed value need to be a multiple
85      of 290, or will round down. Range 0~31*290.
86
87  mediatek,rmii-rxc:
88    type: boolean
89    description:
90      If present, indicates that the RMII reference clock, which is from external
91      PHYs, is connected to RXC pin. Otherwise, is connected to TXC pin.
92
93  mediatek,rmii-clk-from-mac:
94    type: boolean
95    description:
96      If present, indicates that MAC provides the RMII reference clock, which
97      outputs to TXC pin only.
98
99  mediatek,txc-inverse:
100    type: boolean
101    description:
102      If present, indicates that
103      1. tx clock will be inversed in MII/RGMII case,
104      2. tx clock inside MAC will be inversed relative to reference clock
105         which is from external PHYs in RMII case, and it rarely happen.
106      3. the reference clock, which outputs to TXC pin will be inversed in RMII case
107         when the reference clock is from MAC.
108
109  mediatek,rxc-inverse:
110    type: boolean
111    description:
112      If present, indicates that
113      1. rx clock will be inversed in MII/RGMII case.
114      2. reference clock will be inversed when arrived at MAC in RMII case, when
115         the reference clock is from external PHYs.
116      3. the inside clock, which be sent to MAC, will be inversed in RMII case when
117         the reference clock is from MAC.
118
119  mediatek,mac-wol:
120    type: boolean
121    description:
122      If present, indicates that MAC supports WOL(Wake-On-LAN), and MAC WOL will be enabled.
123      Otherwise, PHY WOL is perferred.
124
125required:
126  - compatible
127  - reg
128  - interrupts
129  - interrupt-names
130  - clocks
131  - clock-names
132  - phy-mode
133  - mediatek,pericfg
134
135unevaluatedProperties: false
136
137examples:
138  - |
139    #include <dt-bindings/clock/mt2712-clk.h>
140    #include <dt-bindings/gpio/gpio.h>
141    #include <dt-bindings/interrupt-controller/arm-gic.h>
142    #include <dt-bindings/interrupt-controller/irq.h>
143    #include <dt-bindings/power/mt2712-power.h>
144
145    eth: ethernet@1101c000 {
146        compatible = "mediatek,mt2712-gmac", "snps,dwmac-4.20a";
147        reg = <0x1101c000 0x1300>;
148        interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_LOW>;
149        interrupt-names = "macirq";
150        phy-mode ="rgmii-rxid";
151        mac-address = [00 55 7b b5 7d f7];
152        clock-names = "axi",
153                      "apb",
154                      "mac_main",
155                      "ptp_ref",
156                      "rmii_internal";
157        clocks = <&pericfg CLK_PERI_GMAC>,
158                 <&pericfg CLK_PERI_GMAC_PCLK>,
159                 <&topckgen CLK_TOP_ETHER_125M_SEL>,
160                 <&topckgen CLK_TOP_ETHER_50M_SEL>,
161                 <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>;
162        assigned-clocks = <&topckgen CLK_TOP_ETHER_125M_SEL>,
163                          <&topckgen CLK_TOP_ETHER_50M_SEL>,
164                          <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>;
165        assigned-clock-parents = <&topckgen CLK_TOP_ETHERPLL_125M>,
166                                 <&topckgen CLK_TOP_APLL1_D3>,
167                                 <&topckgen CLK_TOP_ETHERPLL_50M>;
168        power-domains = <&scpsys MT2712_POWER_DOMAIN_AUDIO>;
169        mediatek,pericfg = <&pericfg>;
170        mediatek,tx-delay-ps = <1530>;
171        snps,txpbl = <1>;
172        snps,rxpbl = <1>;
173        snps,reset-gpio = <&pio 87 GPIO_ACTIVE_LOW>;
174        snps,reset-delays-us = <0 10000 10000>;
175    };
176