1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/mediatek,net.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MediaTek Frame Engine Ethernet controller
8
9maintainers:
10  - Lorenzo Bianconi <lorenzo@kernel.org>
11  - Felix Fietkau <nbd@nbd.name>
12
13description:
14  The frame engine ethernet controller can be found on MediaTek SoCs. These SoCs
15  have dual GMAC ports.
16
17properties:
18  compatible:
19    enum:
20      - mediatek,mt2701-eth
21      - mediatek,mt7623-eth
22      - mediatek,mt7622-eth
23      - mediatek,mt7629-eth
24      - ralink,rt5350-eth
25
26  reg:
27    maxItems: 1
28
29  interrupts:
30    minItems: 3
31    maxItems: 3
32
33  power-domains:
34    maxItems: 1
35
36  resets:
37    maxItems: 3
38
39  reset-names:
40    items:
41      - const: fe
42      - const: gmac
43      - const: ppe
44
45  mediatek,ethsys:
46    $ref: /schemas/types.yaml#/definitions/phandle
47    description:
48      Phandle to the syscon node that handles the port setup.
49
50  cci-control-port: true
51
52  mediatek,hifsys:
53    $ref: /schemas/types.yaml#/definitions/phandle
54    description:
55      Phandle to the mediatek hifsys controller used to provide various clocks
56      and reset to the system.
57
58  mediatek,sgmiisys:
59    $ref: /schemas/types.yaml#/definitions/phandle-array
60    minItems: 1
61    maxItems: 2
62    items:
63      maxItems: 1
64    description:
65      A list of phandle to the syscon node that handles the SGMII setup which is required for
66      those SoCs equipped with SGMII.
67
68  dma-coherent: true
69
70  mdio-bus:
71    $ref: mdio.yaml#
72    unevaluatedProperties: false
73
74  "#address-cells":
75    const: 1
76
77  "#size-cells":
78    const: 0
79
80allOf:
81  - $ref: "ethernet-controller.yaml#"
82  - if:
83      properties:
84        compatible:
85          contains:
86            enum:
87              - mediatek,mt2701-eth
88              - mediatek,mt7623-eth
89    then:
90      properties:
91        clocks:
92          minItems: 4
93          maxItems: 4
94
95        clock-names:
96          items:
97            - const: ethif
98            - const: esw
99            - const: gp1
100            - const: gp2
101
102        mediatek,pctl:
103          $ref: /schemas/types.yaml#/definitions/phandle
104          description:
105            Phandle to the syscon node that handles the ports slew rate and
106            driver current.
107
108  - if:
109      properties:
110        compatible:
111          contains:
112            const: mediatek,mt7622-eth
113    then:
114      properties:
115        clocks:
116          minItems: 11
117          maxItems: 11
118
119        clock-names:
120          items:
121            - const: ethif
122            - const: esw
123            - const: gp0
124            - const: gp1
125            - const: gp2
126            - const: sgmii_tx250m
127            - const: sgmii_rx250m
128            - const: sgmii_cdr_ref
129            - const: sgmii_cdr_fb
130            - const: sgmii_ck
131            - const: eth2pll
132
133        mediatek,sgmiisys:
134          minItems: 1
135          maxItems: 1
136
137        mediatek,wed:
138          $ref: /schemas/types.yaml#/definitions/phandle-array
139          minItems: 2
140          maxItems: 2
141          items:
142            maxItems: 1
143          description:
144            List of phandles to wireless ethernet dispatch nodes.
145
146        mediatek,pcie-mirror:
147          $ref: /schemas/types.yaml#/definitions/phandle
148          description:
149            Phandle to the mediatek pcie-mirror controller.
150
151  - if:
152      properties:
153        compatible:
154          contains:
155            const: mediatek,mt7629-eth
156    then:
157      properties:
158        clocks:
159          minItems: 17
160          maxItems: 17
161
162        clock-names:
163          items:
164            - const: ethif
165            - const: sgmiitop
166            - const: esw
167            - const: gp0
168            - const: gp1
169            - const: gp2
170            - const: fe
171            - const: sgmii_tx250m
172            - const: sgmii_rx250m
173            - const: sgmii_cdr_ref
174            - const: sgmii_cdr_fb
175            - const: sgmii2_tx250m
176            - const: sgmii2_rx250m
177            - const: sgmii2_cdr_ref
178            - const: sgmii2_cdr_fb
179            - const: sgmii_ck
180            - const: eth2pll
181
182        mediatek,infracfg:
183          $ref: /schemas/types.yaml#/definitions/phandle
184          description:
185            Phandle to the syscon node that handles the path from GMAC to
186            PHY variants.
187
188        mediatek,sgmiisys:
189          minItems: 2
190          maxItems: 2
191
192patternProperties:
193  "^mac@[0-1]$":
194    type: object
195    additionalProperties: false
196    allOf:
197      - $ref: ethernet-controller.yaml#
198    description:
199      Ethernet MAC node
200    properties:
201      compatible:
202        const: mediatek,eth-mac
203
204      reg:
205        maxItems: 1
206
207      phy-handle: true
208
209      phy-mode: true
210
211    required:
212      - reg
213      - compatible
214      - phy-handle
215
216required:
217  - compatible
218  - reg
219  - interrupts
220  - clocks
221  - clock-names
222  - power-domains
223  - mediatek,ethsys
224
225unevaluatedProperties: false
226
227examples:
228  - |
229    #include <dt-bindings/interrupt-controller/arm-gic.h>
230    #include <dt-bindings/interrupt-controller/irq.h>
231    #include <dt-bindings/clock/mt7622-clk.h>
232    #include <dt-bindings/power/mt7622-power.h>
233
234    soc {
235      #address-cells = <2>;
236      #size-cells = <2>;
237
238      ethernet: ethernet@1b100000 {
239        compatible = "mediatek,mt7622-eth";
240        reg = <0 0x1b100000 0 0x20000>;
241        interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_LOW>,
242                     <GIC_SPI 224 IRQ_TYPE_LEVEL_LOW>,
243                     <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
244        clocks = <&topckgen CLK_TOP_ETH_SEL>,
245                 <&ethsys CLK_ETH_ESW_EN>,
246                 <&ethsys CLK_ETH_GP0_EN>,
247                 <&ethsys CLK_ETH_GP1_EN>,
248                 <&ethsys CLK_ETH_GP2_EN>,
249                 <&sgmiisys CLK_SGMII_TX250M_EN>,
250                 <&sgmiisys CLK_SGMII_RX250M_EN>,
251                 <&sgmiisys CLK_SGMII_CDR_REF>,
252                 <&sgmiisys CLK_SGMII_CDR_FB>,
253                 <&topckgen CLK_TOP_SGMIIPLL>,
254                 <&apmixedsys CLK_APMIXED_ETH2PLL>;
255        clock-names = "ethif", "esw", "gp0", "gp1", "gp2",
256                      "sgmii_tx250m", "sgmii_rx250m",
257                      "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck",
258                      "eth2pll";
259        power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
260        mediatek,ethsys = <&ethsys>;
261        mediatek,sgmiisys = <&sgmiisys>;
262        cci-control-port = <&cci_control2>;
263        mediatek,pcie-mirror = <&pcie_mirror>;
264        mediatek,hifsys = <&hifsys>;
265        dma-coherent;
266
267        #address-cells = <1>;
268        #size-cells = <0>;
269
270        mdio0: mdio-bus {
271          #address-cells = <1>;
272          #size-cells = <0>;
273
274          phy0: ethernet-phy@0 {
275            reg = <0>;
276          };
277
278          phy1: ethernet-phy@1 {
279            reg = <1>;
280          };
281        };
282
283        gmac0: mac@0 {
284          compatible = "mediatek,eth-mac";
285          phy-mode = "rgmii";
286          phy-handle = <&phy0>;
287          reg = <0>;
288        };
289
290        gmac1: mac@1 {
291          compatible = "mediatek,eth-mac";
292          phy-mode = "rgmii";
293          phy-handle = <&phy1>;
294          reg = <1>;
295        };
296      };
297    };
298