1c78c5a66SLorenzo Bianconi# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2c78c5a66SLorenzo Bianconi%YAML 1.2 3c78c5a66SLorenzo Bianconi--- 4c78c5a66SLorenzo Bianconi$id: http://devicetree.org/schemas/net/mediatek,net.yaml# 5c78c5a66SLorenzo Bianconi$schema: http://devicetree.org/meta-schemas/core.yaml# 6c78c5a66SLorenzo Bianconi 7c78c5a66SLorenzo Bianconititle: MediaTek Frame Engine Ethernet controller 8c78c5a66SLorenzo Bianconi 9c78c5a66SLorenzo Bianconimaintainers: 10c78c5a66SLorenzo Bianconi - Lorenzo Bianconi <lorenzo@kernel.org> 11c78c5a66SLorenzo Bianconi - Felix Fietkau <nbd@nbd.name> 12c78c5a66SLorenzo Bianconi 13c78c5a66SLorenzo Bianconidescription: 14c78c5a66SLorenzo Bianconi The frame engine ethernet controller can be found on MediaTek SoCs. These SoCs 15c78c5a66SLorenzo Bianconi have dual GMAC ports. 16c78c5a66SLorenzo Bianconi 17c78c5a66SLorenzo Bianconiproperties: 18c78c5a66SLorenzo Bianconi compatible: 19c78c5a66SLorenzo Bianconi enum: 20c78c5a66SLorenzo Bianconi - mediatek,mt2701-eth 21c78c5a66SLorenzo Bianconi - mediatek,mt7623-eth 22c78c5a66SLorenzo Bianconi - mediatek,mt7622-eth 23c78c5a66SLorenzo Bianconi - mediatek,mt7629-eth 24*4b139b75SLorenzo Bianconi - mediatek,mt7986-eth 25c78c5a66SLorenzo Bianconi - ralink,rt5350-eth 26c78c5a66SLorenzo Bianconi 27c78c5a66SLorenzo Bianconi reg: 28c78c5a66SLorenzo Bianconi maxItems: 1 29c78c5a66SLorenzo Bianconi 30c78c5a66SLorenzo Bianconi interrupts: 31c78c5a66SLorenzo Bianconi minItems: 3 32*4b139b75SLorenzo Bianconi maxItems: 4 33c78c5a66SLorenzo Bianconi 34c78c5a66SLorenzo Bianconi power-domains: 35c78c5a66SLorenzo Bianconi maxItems: 1 36c78c5a66SLorenzo Bianconi 37c78c5a66SLorenzo Bianconi resets: 38c78c5a66SLorenzo Bianconi maxItems: 3 39c78c5a66SLorenzo Bianconi 40c78c5a66SLorenzo Bianconi reset-names: 41c78c5a66SLorenzo Bianconi items: 42c78c5a66SLorenzo Bianconi - const: fe 43c78c5a66SLorenzo Bianconi - const: gmac 44c78c5a66SLorenzo Bianconi - const: ppe 45c78c5a66SLorenzo Bianconi 46c78c5a66SLorenzo Bianconi mediatek,ethsys: 47c78c5a66SLorenzo Bianconi $ref: /schemas/types.yaml#/definitions/phandle 48c78c5a66SLorenzo Bianconi description: 49c78c5a66SLorenzo Bianconi Phandle to the syscon node that handles the port setup. 50c78c5a66SLorenzo Bianconi 51c78c5a66SLorenzo Bianconi cci-control-port: true 52c78c5a66SLorenzo Bianconi 53c78c5a66SLorenzo Bianconi mediatek,hifsys: 54c78c5a66SLorenzo Bianconi $ref: /schemas/types.yaml#/definitions/phandle 55c78c5a66SLorenzo Bianconi description: 56c78c5a66SLorenzo Bianconi Phandle to the mediatek hifsys controller used to provide various clocks 57c78c5a66SLorenzo Bianconi and reset to the system. 58c78c5a66SLorenzo Bianconi 59c78c5a66SLorenzo Bianconi mediatek,sgmiisys: 60c78c5a66SLorenzo Bianconi $ref: /schemas/types.yaml#/definitions/phandle-array 61c78c5a66SLorenzo Bianconi minItems: 1 62c78c5a66SLorenzo Bianconi maxItems: 2 63c78c5a66SLorenzo Bianconi items: 64c78c5a66SLorenzo Bianconi maxItems: 1 65c78c5a66SLorenzo Bianconi description: 66c78c5a66SLorenzo Bianconi A list of phandle to the syscon node that handles the SGMII setup which is required for 67c78c5a66SLorenzo Bianconi those SoCs equipped with SGMII. 68c78c5a66SLorenzo Bianconi 69c78c5a66SLorenzo Bianconi dma-coherent: true 70c78c5a66SLorenzo Bianconi 71c78c5a66SLorenzo Bianconi mdio-bus: 72c78c5a66SLorenzo Bianconi $ref: mdio.yaml# 73c78c5a66SLorenzo Bianconi unevaluatedProperties: false 74c78c5a66SLorenzo Bianconi 75c78c5a66SLorenzo Bianconi "#address-cells": 76c78c5a66SLorenzo Bianconi const: 1 77c78c5a66SLorenzo Bianconi 78c78c5a66SLorenzo Bianconi "#size-cells": 79c78c5a66SLorenzo Bianconi const: 0 80c78c5a66SLorenzo Bianconi 81c78c5a66SLorenzo BianconiallOf: 82c78c5a66SLorenzo Bianconi - $ref: "ethernet-controller.yaml#" 83c78c5a66SLorenzo Bianconi - if: 84c78c5a66SLorenzo Bianconi properties: 85c78c5a66SLorenzo Bianconi compatible: 86c78c5a66SLorenzo Bianconi contains: 87c78c5a66SLorenzo Bianconi enum: 88c78c5a66SLorenzo Bianconi - mediatek,mt2701-eth 89c78c5a66SLorenzo Bianconi - mediatek,mt7623-eth 90c78c5a66SLorenzo Bianconi then: 91c78c5a66SLorenzo Bianconi properties: 92*4b139b75SLorenzo Bianconi interrupts: 93*4b139b75SLorenzo Bianconi maxItems: 3 94*4b139b75SLorenzo Bianconi 95c78c5a66SLorenzo Bianconi clocks: 96c78c5a66SLorenzo Bianconi minItems: 4 97c78c5a66SLorenzo Bianconi maxItems: 4 98c78c5a66SLorenzo Bianconi 99c78c5a66SLorenzo Bianconi clock-names: 100c78c5a66SLorenzo Bianconi items: 101c78c5a66SLorenzo Bianconi - const: ethif 102c78c5a66SLorenzo Bianconi - const: esw 103c78c5a66SLorenzo Bianconi - const: gp1 104c78c5a66SLorenzo Bianconi - const: gp2 105c78c5a66SLorenzo Bianconi 106c78c5a66SLorenzo Bianconi mediatek,pctl: 107c78c5a66SLorenzo Bianconi $ref: /schemas/types.yaml#/definitions/phandle 108c78c5a66SLorenzo Bianconi description: 109c78c5a66SLorenzo Bianconi Phandle to the syscon node that handles the ports slew rate and 110c78c5a66SLorenzo Bianconi driver current. 111c78c5a66SLorenzo Bianconi 112c78c5a66SLorenzo Bianconi - if: 113c78c5a66SLorenzo Bianconi properties: 114c78c5a66SLorenzo Bianconi compatible: 115c78c5a66SLorenzo Bianconi contains: 116c78c5a66SLorenzo Bianconi const: mediatek,mt7622-eth 117c78c5a66SLorenzo Bianconi then: 118c78c5a66SLorenzo Bianconi properties: 119*4b139b75SLorenzo Bianconi interrupts: 120*4b139b75SLorenzo Bianconi maxItems: 3 121*4b139b75SLorenzo Bianconi 122c78c5a66SLorenzo Bianconi clocks: 123c78c5a66SLorenzo Bianconi minItems: 11 124c78c5a66SLorenzo Bianconi maxItems: 11 125c78c5a66SLorenzo Bianconi 126c78c5a66SLorenzo Bianconi clock-names: 127c78c5a66SLorenzo Bianconi items: 128c78c5a66SLorenzo Bianconi - const: ethif 129c78c5a66SLorenzo Bianconi - const: esw 130c78c5a66SLorenzo Bianconi - const: gp0 131c78c5a66SLorenzo Bianconi - const: gp1 132c78c5a66SLorenzo Bianconi - const: gp2 133c78c5a66SLorenzo Bianconi - const: sgmii_tx250m 134c78c5a66SLorenzo Bianconi - const: sgmii_rx250m 135c78c5a66SLorenzo Bianconi - const: sgmii_cdr_ref 136c78c5a66SLorenzo Bianconi - const: sgmii_cdr_fb 137c78c5a66SLorenzo Bianconi - const: sgmii_ck 138c78c5a66SLorenzo Bianconi - const: eth2pll 139c78c5a66SLorenzo Bianconi 140c78c5a66SLorenzo Bianconi mediatek,sgmiisys: 141c78c5a66SLorenzo Bianconi minItems: 1 142c78c5a66SLorenzo Bianconi maxItems: 1 143c78c5a66SLorenzo Bianconi 144c78c5a66SLorenzo Bianconi mediatek,wed: 145c78c5a66SLorenzo Bianconi $ref: /schemas/types.yaml#/definitions/phandle-array 146c78c5a66SLorenzo Bianconi minItems: 2 147c78c5a66SLorenzo Bianconi maxItems: 2 148c78c5a66SLorenzo Bianconi items: 149c78c5a66SLorenzo Bianconi maxItems: 1 150c78c5a66SLorenzo Bianconi description: 151c78c5a66SLorenzo Bianconi List of phandles to wireless ethernet dispatch nodes. 152c78c5a66SLorenzo Bianconi 153c78c5a66SLorenzo Bianconi mediatek,pcie-mirror: 154c78c5a66SLorenzo Bianconi $ref: /schemas/types.yaml#/definitions/phandle 155c78c5a66SLorenzo Bianconi description: 156c78c5a66SLorenzo Bianconi Phandle to the mediatek pcie-mirror controller. 157c78c5a66SLorenzo Bianconi 158c78c5a66SLorenzo Bianconi - if: 159c78c5a66SLorenzo Bianconi properties: 160c78c5a66SLorenzo Bianconi compatible: 161c78c5a66SLorenzo Bianconi contains: 162c78c5a66SLorenzo Bianconi const: mediatek,mt7629-eth 163c78c5a66SLorenzo Bianconi then: 164c78c5a66SLorenzo Bianconi properties: 165*4b139b75SLorenzo Bianconi interrupts: 166*4b139b75SLorenzo Bianconi maxItems: 3 167*4b139b75SLorenzo Bianconi 168c78c5a66SLorenzo Bianconi clocks: 169c78c5a66SLorenzo Bianconi minItems: 17 170c78c5a66SLorenzo Bianconi maxItems: 17 171c78c5a66SLorenzo Bianconi 172c78c5a66SLorenzo Bianconi clock-names: 173c78c5a66SLorenzo Bianconi items: 174c78c5a66SLorenzo Bianconi - const: ethif 175c78c5a66SLorenzo Bianconi - const: sgmiitop 176c78c5a66SLorenzo Bianconi - const: esw 177c78c5a66SLorenzo Bianconi - const: gp0 178c78c5a66SLorenzo Bianconi - const: gp1 179c78c5a66SLorenzo Bianconi - const: gp2 180c78c5a66SLorenzo Bianconi - const: fe 181c78c5a66SLorenzo Bianconi - const: sgmii_tx250m 182c78c5a66SLorenzo Bianconi - const: sgmii_rx250m 183c78c5a66SLorenzo Bianconi - const: sgmii_cdr_ref 184c78c5a66SLorenzo Bianconi - const: sgmii_cdr_fb 185c78c5a66SLorenzo Bianconi - const: sgmii2_tx250m 186c78c5a66SLorenzo Bianconi - const: sgmii2_rx250m 187c78c5a66SLorenzo Bianconi - const: sgmii2_cdr_ref 188c78c5a66SLorenzo Bianconi - const: sgmii2_cdr_fb 189c78c5a66SLorenzo Bianconi - const: sgmii_ck 190c78c5a66SLorenzo Bianconi - const: eth2pll 191c78c5a66SLorenzo Bianconi 192c78c5a66SLorenzo Bianconi mediatek,infracfg: 193c78c5a66SLorenzo Bianconi $ref: /schemas/types.yaml#/definitions/phandle 194c78c5a66SLorenzo Bianconi description: 195c78c5a66SLorenzo Bianconi Phandle to the syscon node that handles the path from GMAC to 196c78c5a66SLorenzo Bianconi PHY variants. 197c78c5a66SLorenzo Bianconi 198c78c5a66SLorenzo Bianconi mediatek,sgmiisys: 199c78c5a66SLorenzo Bianconi minItems: 2 200c78c5a66SLorenzo Bianconi maxItems: 2 201c78c5a66SLorenzo Bianconi 202*4b139b75SLorenzo Bianconi - if: 203*4b139b75SLorenzo Bianconi properties: 204*4b139b75SLorenzo Bianconi compatible: 205*4b139b75SLorenzo Bianconi contains: 206*4b139b75SLorenzo Bianconi const: mediatek,mt7986-eth 207*4b139b75SLorenzo Bianconi then: 208*4b139b75SLorenzo Bianconi properties: 209*4b139b75SLorenzo Bianconi interrupts: 210*4b139b75SLorenzo Bianconi minItems: 4 211*4b139b75SLorenzo Bianconi 212*4b139b75SLorenzo Bianconi clocks: 213*4b139b75SLorenzo Bianconi minItems: 15 214*4b139b75SLorenzo Bianconi maxItems: 15 215*4b139b75SLorenzo Bianconi 216*4b139b75SLorenzo Bianconi clock-names: 217*4b139b75SLorenzo Bianconi items: 218*4b139b75SLorenzo Bianconi - const: fe 219*4b139b75SLorenzo Bianconi - const: gp2 220*4b139b75SLorenzo Bianconi - const: gp1 221*4b139b75SLorenzo Bianconi - const: wocpu1 222*4b139b75SLorenzo Bianconi - const: wocpu0 223*4b139b75SLorenzo Bianconi - const: sgmii_tx250m 224*4b139b75SLorenzo Bianconi - const: sgmii_rx250m 225*4b139b75SLorenzo Bianconi - const: sgmii_cdr_ref 226*4b139b75SLorenzo Bianconi - const: sgmii_cdr_fb 227*4b139b75SLorenzo Bianconi - const: sgmii2_tx250m 228*4b139b75SLorenzo Bianconi - const: sgmii2_rx250m 229*4b139b75SLorenzo Bianconi - const: sgmii2_cdr_ref 230*4b139b75SLorenzo Bianconi - const: sgmii2_cdr_fb 231*4b139b75SLorenzo Bianconi - const: netsys0 232*4b139b75SLorenzo Bianconi - const: netsys1 233*4b139b75SLorenzo Bianconi 234*4b139b75SLorenzo Bianconi mediatek,sgmiisys: 235*4b139b75SLorenzo Bianconi minItems: 2 236*4b139b75SLorenzo Bianconi maxItems: 2 237*4b139b75SLorenzo Bianconi 238c78c5a66SLorenzo BianconipatternProperties: 239c78c5a66SLorenzo Bianconi "^mac@[0-1]$": 240c78c5a66SLorenzo Bianconi type: object 241c78c5a66SLorenzo Bianconi additionalProperties: false 242c78c5a66SLorenzo Bianconi allOf: 243c78c5a66SLorenzo Bianconi - $ref: ethernet-controller.yaml# 244c78c5a66SLorenzo Bianconi description: 245c78c5a66SLorenzo Bianconi Ethernet MAC node 246c78c5a66SLorenzo Bianconi properties: 247c78c5a66SLorenzo Bianconi compatible: 248c78c5a66SLorenzo Bianconi const: mediatek,eth-mac 249c78c5a66SLorenzo Bianconi 250c78c5a66SLorenzo Bianconi reg: 251c78c5a66SLorenzo Bianconi maxItems: 1 252c78c5a66SLorenzo Bianconi 253c78c5a66SLorenzo Bianconi phy-handle: true 254c78c5a66SLorenzo Bianconi 255c78c5a66SLorenzo Bianconi phy-mode: true 256c78c5a66SLorenzo Bianconi 257c78c5a66SLorenzo Bianconi required: 258c78c5a66SLorenzo Bianconi - reg 259c78c5a66SLorenzo Bianconi - compatible 260c78c5a66SLorenzo Bianconi - phy-handle 261c78c5a66SLorenzo Bianconi 262c78c5a66SLorenzo Bianconirequired: 263c78c5a66SLorenzo Bianconi - compatible 264c78c5a66SLorenzo Bianconi - reg 265c78c5a66SLorenzo Bianconi - interrupts 266c78c5a66SLorenzo Bianconi - clocks 267c78c5a66SLorenzo Bianconi - clock-names 268c78c5a66SLorenzo Bianconi - mediatek,ethsys 269c78c5a66SLorenzo Bianconi 270c78c5a66SLorenzo BianconiunevaluatedProperties: false 271c78c5a66SLorenzo Bianconi 272c78c5a66SLorenzo Bianconiexamples: 273c78c5a66SLorenzo Bianconi - | 274c78c5a66SLorenzo Bianconi #include <dt-bindings/interrupt-controller/arm-gic.h> 275c78c5a66SLorenzo Bianconi #include <dt-bindings/interrupt-controller/irq.h> 276c78c5a66SLorenzo Bianconi #include <dt-bindings/clock/mt7622-clk.h> 277c78c5a66SLorenzo Bianconi #include <dt-bindings/power/mt7622-power.h> 278c78c5a66SLorenzo Bianconi 279c78c5a66SLorenzo Bianconi soc { 280c78c5a66SLorenzo Bianconi #address-cells = <2>; 281c78c5a66SLorenzo Bianconi #size-cells = <2>; 282c78c5a66SLorenzo Bianconi 283c78c5a66SLorenzo Bianconi ethernet: ethernet@1b100000 { 284c78c5a66SLorenzo Bianconi compatible = "mediatek,mt7622-eth"; 285c78c5a66SLorenzo Bianconi reg = <0 0x1b100000 0 0x20000>; 286c78c5a66SLorenzo Bianconi interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_LOW>, 287c78c5a66SLorenzo Bianconi <GIC_SPI 224 IRQ_TYPE_LEVEL_LOW>, 288c78c5a66SLorenzo Bianconi <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>; 289c78c5a66SLorenzo Bianconi clocks = <&topckgen CLK_TOP_ETH_SEL>, 290c78c5a66SLorenzo Bianconi <ðsys CLK_ETH_ESW_EN>, 291c78c5a66SLorenzo Bianconi <ðsys CLK_ETH_GP0_EN>, 292c78c5a66SLorenzo Bianconi <ðsys CLK_ETH_GP1_EN>, 293c78c5a66SLorenzo Bianconi <ðsys CLK_ETH_GP2_EN>, 294c78c5a66SLorenzo Bianconi <&sgmiisys CLK_SGMII_TX250M_EN>, 295c78c5a66SLorenzo Bianconi <&sgmiisys CLK_SGMII_RX250M_EN>, 296c78c5a66SLorenzo Bianconi <&sgmiisys CLK_SGMII_CDR_REF>, 297c78c5a66SLorenzo Bianconi <&sgmiisys CLK_SGMII_CDR_FB>, 298c78c5a66SLorenzo Bianconi <&topckgen CLK_TOP_SGMIIPLL>, 299c78c5a66SLorenzo Bianconi <&apmixedsys CLK_APMIXED_ETH2PLL>; 300c78c5a66SLorenzo Bianconi clock-names = "ethif", "esw", "gp0", "gp1", "gp2", 301c78c5a66SLorenzo Bianconi "sgmii_tx250m", "sgmii_rx250m", 302c78c5a66SLorenzo Bianconi "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck", 303c78c5a66SLorenzo Bianconi "eth2pll"; 304c78c5a66SLorenzo Bianconi power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>; 305c78c5a66SLorenzo Bianconi mediatek,ethsys = <ðsys>; 306c78c5a66SLorenzo Bianconi mediatek,sgmiisys = <&sgmiisys>; 307c78c5a66SLorenzo Bianconi cci-control-port = <&cci_control2>; 308c78c5a66SLorenzo Bianconi mediatek,pcie-mirror = <&pcie_mirror>; 309c78c5a66SLorenzo Bianconi mediatek,hifsys = <&hifsys>; 310c78c5a66SLorenzo Bianconi dma-coherent; 311c78c5a66SLorenzo Bianconi 312c78c5a66SLorenzo Bianconi #address-cells = <1>; 313c78c5a66SLorenzo Bianconi #size-cells = <0>; 314c78c5a66SLorenzo Bianconi 315c78c5a66SLorenzo Bianconi mdio0: mdio-bus { 316c78c5a66SLorenzo Bianconi #address-cells = <1>; 317c78c5a66SLorenzo Bianconi #size-cells = <0>; 318c78c5a66SLorenzo Bianconi 319c78c5a66SLorenzo Bianconi phy0: ethernet-phy@0 { 320c78c5a66SLorenzo Bianconi reg = <0>; 321c78c5a66SLorenzo Bianconi }; 322c78c5a66SLorenzo Bianconi 323c78c5a66SLorenzo Bianconi phy1: ethernet-phy@1 { 324c78c5a66SLorenzo Bianconi reg = <1>; 325c78c5a66SLorenzo Bianconi }; 326c78c5a66SLorenzo Bianconi }; 327c78c5a66SLorenzo Bianconi 328c78c5a66SLorenzo Bianconi gmac0: mac@0 { 329c78c5a66SLorenzo Bianconi compatible = "mediatek,eth-mac"; 330c78c5a66SLorenzo Bianconi phy-mode = "rgmii"; 331c78c5a66SLorenzo Bianconi phy-handle = <&phy0>; 332c78c5a66SLorenzo Bianconi reg = <0>; 333c78c5a66SLorenzo Bianconi }; 334c78c5a66SLorenzo Bianconi 335c78c5a66SLorenzo Bianconi gmac1: mac@1 { 336c78c5a66SLorenzo Bianconi compatible = "mediatek,eth-mac"; 337c78c5a66SLorenzo Bianconi phy-mode = "rgmii"; 338c78c5a66SLorenzo Bianconi phy-handle = <&phy1>; 339c78c5a66SLorenzo Bianconi reg = <1>; 340c78c5a66SLorenzo Bianconi }; 341c78c5a66SLorenzo Bianconi }; 342c78c5a66SLorenzo Bianconi }; 343*4b139b75SLorenzo Bianconi 344*4b139b75SLorenzo Bianconi - | 345*4b139b75SLorenzo Bianconi #include <dt-bindings/interrupt-controller/arm-gic.h> 346*4b139b75SLorenzo Bianconi #include <dt-bindings/interrupt-controller/irq.h> 347*4b139b75SLorenzo Bianconi #include <dt-bindings/clock/mt7622-clk.h> 348*4b139b75SLorenzo Bianconi 349*4b139b75SLorenzo Bianconi soc { 350*4b139b75SLorenzo Bianconi #address-cells = <2>; 351*4b139b75SLorenzo Bianconi #size-cells = <2>; 352*4b139b75SLorenzo Bianconi 353*4b139b75SLorenzo Bianconi eth: ethernet@15100000 { 354*4b139b75SLorenzo Bianconi #define CLK_ETH_FE_EN 0 355*4b139b75SLorenzo Bianconi #define CLK_ETH_WOCPU1_EN 3 356*4b139b75SLorenzo Bianconi #define CLK_ETH_WOCPU0_EN 4 357*4b139b75SLorenzo Bianconi #define CLK_TOP_NETSYS_SEL 43 358*4b139b75SLorenzo Bianconi #define CLK_TOP_NETSYS_500M_SEL 44 359*4b139b75SLorenzo Bianconi #define CLK_TOP_NETSYS_2X_SEL 46 360*4b139b75SLorenzo Bianconi #define CLK_TOP_SGM_325M_SEL 47 361*4b139b75SLorenzo Bianconi #define CLK_APMIXED_NET2PLL 1 362*4b139b75SLorenzo Bianconi #define CLK_APMIXED_SGMPLL 3 363*4b139b75SLorenzo Bianconi 364*4b139b75SLorenzo Bianconi compatible = "mediatek,mt7986-eth"; 365*4b139b75SLorenzo Bianconi reg = <0 0x15100000 0 0x80000>; 366*4b139b75SLorenzo Bianconi interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 367*4b139b75SLorenzo Bianconi <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, 368*4b139b75SLorenzo Bianconi <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, 369*4b139b75SLorenzo Bianconi <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 370*4b139b75SLorenzo Bianconi clocks = <ðsys CLK_ETH_FE_EN>, 371*4b139b75SLorenzo Bianconi <ðsys CLK_ETH_GP2_EN>, 372*4b139b75SLorenzo Bianconi <ðsys CLK_ETH_GP1_EN>, 373*4b139b75SLorenzo Bianconi <ðsys CLK_ETH_WOCPU1_EN>, 374*4b139b75SLorenzo Bianconi <ðsys CLK_ETH_WOCPU0_EN>, 375*4b139b75SLorenzo Bianconi <&sgmiisys0 CLK_SGMII_TX250M_EN>, 376*4b139b75SLorenzo Bianconi <&sgmiisys0 CLK_SGMII_RX250M_EN>, 377*4b139b75SLorenzo Bianconi <&sgmiisys0 CLK_SGMII_CDR_REF>, 378*4b139b75SLorenzo Bianconi <&sgmiisys0 CLK_SGMII_CDR_FB>, 379*4b139b75SLorenzo Bianconi <&sgmiisys1 CLK_SGMII_TX250M_EN>, 380*4b139b75SLorenzo Bianconi <&sgmiisys1 CLK_SGMII_RX250M_EN>, 381*4b139b75SLorenzo Bianconi <&sgmiisys1 CLK_SGMII_CDR_REF>, 382*4b139b75SLorenzo Bianconi <&sgmiisys1 CLK_SGMII_CDR_FB>, 383*4b139b75SLorenzo Bianconi <&topckgen CLK_TOP_NETSYS_SEL>, 384*4b139b75SLorenzo Bianconi <&topckgen CLK_TOP_NETSYS_SEL>; 385*4b139b75SLorenzo Bianconi clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0", 386*4b139b75SLorenzo Bianconi "sgmii_tx250m", "sgmii_rx250m", 387*4b139b75SLorenzo Bianconi "sgmii_cdr_ref", "sgmii_cdr_fb", 388*4b139b75SLorenzo Bianconi "sgmii2_tx250m", "sgmii2_rx250m", 389*4b139b75SLorenzo Bianconi "sgmii2_cdr_ref", "sgmii2_cdr_fb", 390*4b139b75SLorenzo Bianconi "netsys0", "netsys1"; 391*4b139b75SLorenzo Bianconi mediatek,ethsys = <ðsys>; 392*4b139b75SLorenzo Bianconi mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>; 393*4b139b75SLorenzo Bianconi assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>, 394*4b139b75SLorenzo Bianconi <&topckgen CLK_TOP_SGM_325M_SEL>; 395*4b139b75SLorenzo Bianconi assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>, 396*4b139b75SLorenzo Bianconi <&apmixedsys CLK_APMIXED_SGMPLL>; 397*4b139b75SLorenzo Bianconi 398*4b139b75SLorenzo Bianconi #address-cells = <1>; 399*4b139b75SLorenzo Bianconi #size-cells = <0>; 400*4b139b75SLorenzo Bianconi 401*4b139b75SLorenzo Bianconi mdio: mdio-bus { 402*4b139b75SLorenzo Bianconi #address-cells = <1>; 403*4b139b75SLorenzo Bianconi #size-cells = <0>; 404*4b139b75SLorenzo Bianconi 405*4b139b75SLorenzo Bianconi phy5: ethernet-phy@0 { 406*4b139b75SLorenzo Bianconi compatible = "ethernet-phy-id67c9.de0a"; 407*4b139b75SLorenzo Bianconi phy-mode = "2500base-x"; 408*4b139b75SLorenzo Bianconi reset-gpios = <&pio 6 1>; 409*4b139b75SLorenzo Bianconi reset-deassert-us = <20000>; 410*4b139b75SLorenzo Bianconi reg = <5>; 411*4b139b75SLorenzo Bianconi }; 412*4b139b75SLorenzo Bianconi 413*4b139b75SLorenzo Bianconi phy6: ethernet-phy@1 { 414*4b139b75SLorenzo Bianconi compatible = "ethernet-phy-id67c9.de0a"; 415*4b139b75SLorenzo Bianconi phy-mode = "2500base-x"; 416*4b139b75SLorenzo Bianconi reg = <6>; 417*4b139b75SLorenzo Bianconi }; 418*4b139b75SLorenzo Bianconi }; 419*4b139b75SLorenzo Bianconi 420*4b139b75SLorenzo Bianconi mac0: mac@0 { 421*4b139b75SLorenzo Bianconi compatible = "mediatek,eth-mac"; 422*4b139b75SLorenzo Bianconi phy-mode = "2500base-x"; 423*4b139b75SLorenzo Bianconi phy-handle = <&phy5>; 424*4b139b75SLorenzo Bianconi reg = <0>; 425*4b139b75SLorenzo Bianconi }; 426*4b139b75SLorenzo Bianconi 427*4b139b75SLorenzo Bianconi mac1: mac@1 { 428*4b139b75SLorenzo Bianconi compatible = "mediatek,eth-mac"; 429*4b139b75SLorenzo Bianconi phy-mode = "2500base-x"; 430*4b139b75SLorenzo Bianconi phy-handle = <&phy6>; 431*4b139b75SLorenzo Bianconi reg = <1>; 432*4b139b75SLorenzo Bianconi }; 433*4b139b75SLorenzo Bianconi }; 434*4b139b75SLorenzo Bianconi }; 435