118b4bad3SAntoine Ténart* Marvell PXA168 Ethernet Controller 218b4bad3SAntoine Ténart 318b4bad3SAntoine TénartRequired properties: 418b4bad3SAntoine Ténart- compatible: should be "marvell,pxa168-eth". 518b4bad3SAntoine Ténart- reg: address and length of the register set for the device. 618b4bad3SAntoine Ténart- interrupts: interrupt for the device. 718b4bad3SAntoine Ténart- clocks: pointer to the clock for the device. 818b4bad3SAntoine Ténart 918b4bad3SAntoine TénartOptional properties: 1018b4bad3SAntoine Ténart- port-id: Ethernet port number. Should be '0','1' or '2'. 1118b4bad3SAntoine Ténart- #address-cells: must be 1 when using sub-nodes. 1218b4bad3SAntoine Ténart- #size-cells: must be 0 when using sub-nodes. 1318b4bad3SAntoine Ténart- phy-handle: see ethernet.txt file in the same directory. 1418b4bad3SAntoine Ténart- local-mac-address: see ethernet.txt file in the same directory. 1518b4bad3SAntoine Ténart 1618b4bad3SAntoine TénartSub-nodes: 1718b4bad3SAntoine TénartEach PHY can be represented as a sub-node. This is not mandatory. 1818b4bad3SAntoine Ténart 1918b4bad3SAntoine TénartSub-nodes required properties: 2018b4bad3SAntoine Ténart- reg: the MDIO address of the PHY. 2118b4bad3SAntoine Ténart 2218b4bad3SAntoine TénartExample: 2318b4bad3SAntoine Ténart 2418b4bad3SAntoine Ténart eth0: ethernet@f7b90000 { 2518b4bad3SAntoine Ténart compatible = "marvell,pxa168-eth"; 2618b4bad3SAntoine Ténart reg = <0xf7b90000 0x10000>; 2718b4bad3SAntoine Ténart clocks = <&chip CLKID_GETH0>; 2818b4bad3SAntoine Ténart interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 2918b4bad3SAntoine Ténart #address-cells = <1>; 3018b4bad3SAntoine Ténart #size-cells = <0>; 3118b4bad3SAntoine Ténart phy-handle = <ðphy0>; 3218b4bad3SAntoine Ténart 3318b4bad3SAntoine Ténart ethphy0: ethernet-phy@0 { 3418b4bad3SAntoine Ténart reg = <0>; 3518b4bad3SAntoine Ténart }; 3618b4bad3SAntoine Ténart }; 37