1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/intel,dwmac-plat.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Intel DWMAC glue layer Device Tree Bindings
8
9maintainers:
10  - Vineetha G. Jaya Kumaran <vineetha.g.jaya.kumaran@intel.com>
11
12select:
13  properties:
14    compatible:
15      contains:
16        enum:
17          - intel,keembay-dwmac
18  required:
19    - compatible
20
21allOf:
22  - $ref: "snps,dwmac.yaml#"
23
24properties:
25  compatible:
26    oneOf:
27      - items:
28          - enum:
29              - intel,keembay-dwmac
30          - const: snps,dwmac-4.10a
31
32  clocks:
33    items:
34      - description: GMAC main clock
35      - description: PTP reference clock
36      - description: Tx clock
37
38  clock-names:
39    items:
40      - const: stmmaceth
41      - const: ptp_ref
42      - const: tx_clk
43
44required:
45  - compatible
46  - clocks
47  - clock-names
48
49examples:
50# FIXME: Remove defines and include the correct header file
51# once it is available in mainline.
52  - |
53    #include <dt-bindings/interrupt-controller/arm-gic.h>
54    #include <dt-bindings/interrupt-controller/irq.h>
55    #define MOVISOC_KMB_PSS_GBE
56    #define MOVISOC_KMB_PSS_AUX_GBE_PTP
57    #define MOVISOC_KMB_PSS_AUX_GBE_TX
58
59    stmmac_axi_setup: stmmac-axi-config {
60        snps,lpi_en;
61        snps,wr_osr_lmt = <0x0>;
62        snps,rd_osr_lmt = <0x2>;
63        snps,blen = <0 0 0 0 16 8 4>;
64    };
65
66    mtl_rx_setup: rx-queues-config {
67        snps,rx-queues-to-use = <2>;
68        snps,rx-sched-sp;
69        queue0 {
70            snps,dcb-algorithm;
71            snps,map-to-dma-channel = <0x0>;
72            snps,priority = <0x0>;
73        };
74
75        queue1 {
76            snps,dcb-algorithm;
77            snps,map-to-dma-channel = <0x1>;
78            snps,priority = <0x1>;
79        };
80    };
81
82    mtl_tx_setup: tx-queues-config {
83        snps,tx-queues-to-use = <2>;
84        snps,tx-sched-wrr;
85        queue0 {
86           snps,weight = <0x10>;
87           snps,dcb-algorithm;
88           snps,priority = <0x0>;
89        };
90
91        queue1 {
92            snps,weight = <0x10>;
93            snps,dcb-algorithm;
94            snps,priority = <0x1>;
95        };
96    };
97
98    gmac0: ethernet@3a000000 {
99        compatible = "intel,keembay-dwmac", "snps,dwmac-4.10a";
100        interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
101        interrupt-names = "macirq";
102        reg = <0x3a000000 0x8000>;
103        snps,perfect-filter-entries = <128>;
104        phy-handle = <&eth_phy0>;
105        phy-mode = "rgmii";
106        rx-fifo-depth = <4096>;
107        tx-fifo-depth = <4096>;
108        clock-names = "stmmaceth", "ptp_ref", "tx_clk";
109        clocks = <&scmi_clk MOVISOC_KMB_PSS_GBE>,
110                 <&scmi_clk MOVISOC_KMB_PSS_AUX_GBE_PTP>,
111                 <&scmi_clk MOVISOC_KMB_PSS_AUX_GBE_TX>;
112        snps,pbl = <0x4>;
113        snps,axi-config = <&stmmac_axi_setup>;
114        snps,mtl-rx-config = <&mtl_rx_setup>;
115        snps,mtl-tx-config = <&mtl_tx_setup>;
116        snps,tso;
117        status = "okay";
118
119        mdio0 {
120            #address-cells = <1>;
121            #size-cells = <0>;
122            compatible = "snps,dwmac-mdio";
123
124            ethernet-phy@0 {
125                reg = <0>;
126            };
127        };
128    };
129
130...
131