1d524dac9SGrant Likely* MDIO IO device
2d524dac9SGrant Likely
3d524dac9SGrant LikelyThe MDIO is a bus to which the PHY devices are connected.  For each
4d524dac9SGrant Likelydevice that exists on this bus, a child node should be created.  See
5d524dac9SGrant Likelythe definition of the PHY node in booting-without-of.txt for an example
6d524dac9SGrant Likelyof how to define a PHY.
7d524dac9SGrant Likely
8d524dac9SGrant LikelyRequired properties:
9d524dac9SGrant Likely  - reg : Offset and length of the register set for the device
10d524dac9SGrant Likely  - compatible : Should define the compatible device type for the
11d524dac9SGrant Likely    mdio.  Currently, this is most likely to be "fsl,gianfar-mdio"
12d524dac9SGrant Likely
13d524dac9SGrant LikelyExample:
14d524dac9SGrant Likely
15d524dac9SGrant Likely	mdio@24520 {
16d524dac9SGrant Likely		reg = <24520 20>;
17d524dac9SGrant Likely		compatible = "fsl,gianfar-mdio";
18d524dac9SGrant Likely
19d524dac9SGrant Likely		ethernet-phy@0 {
20d524dac9SGrant Likely			......
21d524dac9SGrant Likely		};
22d524dac9SGrant Likely	};
23d524dac9SGrant Likely
24d524dac9SGrant Likely* TBI Internal MDIO bus
25d524dac9SGrant Likely
26d524dac9SGrant LikelyAs of this writing, every tsec is associated with an internal TBI PHY.
27d524dac9SGrant LikelyThis PHY is accessed through the local MDIO bus.  These buses are defined
28d524dac9SGrant Likelysimilarly to the mdio buses, except they are compatible with "fsl,gianfar-tbi".
29d524dac9SGrant LikelyThe TBI PHYs underneath them are similar to normal PHYs, but the reg property
30d524dac9SGrant Likelyis considered instructive, rather than descriptive.  The reg property should
31d524dac9SGrant Likelybe chosen so it doesn't interfere with other PHYs on the bus.
32d524dac9SGrant Likely
33d524dac9SGrant Likely* Gianfar-compatible ethernet nodes
34d524dac9SGrant Likely
35d524dac9SGrant LikelyProperties:
36d524dac9SGrant Likely
37d524dac9SGrant Likely  - device_type : Should be "network"
38d524dac9SGrant Likely  - model : Model of the device.  Can be "TSEC", "eTSEC", or "FEC"
39d524dac9SGrant Likely  - compatible : Should be "gianfar"
40d524dac9SGrant Likely  - reg : Offset and length of the register set for the device
41d524dac9SGrant Likely  - interrupts : For FEC devices, the first interrupt is the device's
42d524dac9SGrant Likely    interrupt.  For TSEC and eTSEC devices, the first interrupt is
43d524dac9SGrant Likely    transmit, the second is receive, and the third is error.
44e8f08ee0SSergei Shtylyov  - phy-handle : See ethernet.txt file in the same directory.
45d524dac9SGrant Likely  - fixed-link : <a b c d e> where a is emulated phy id - choose any,
46d524dac9SGrant Likely    but unique to the all specified fixed-links, b is duplex - 0 half,
47d524dac9SGrant Likely    1 full, c is link speed - d#10/d#100/d#1000, d is pause - 0 no
48d524dac9SGrant Likely    pause, 1 pause, e is asym_pause - 0 no asym_pause, 1 asym_pause.
49e8f08ee0SSergei Shtylyov  - phy-connection-type : See ethernet.txt file in the same directory.
50e8f08ee0SSergei Shtylyov    This property is only really needed if the connection is of type
51e8f08ee0SSergei Shtylyov    "rgmii-id", as all other connection types are detected by hardware.
52d524dac9SGrant Likely  - fsl,magic-packet : If present, indicates that the hardware supports
53d524dac9SGrant Likely    waking up via magic packet.
54d524dac9SGrant Likely  - bd-stash : If present, indicates that the hardware supports stashing
55d524dac9SGrant Likely    buffer descriptors in the L2.
56d524dac9SGrant Likely  - rx-stash-len : Denotes the number of bytes of a received buffer to stash
57d524dac9SGrant Likely    in the L2.
58d524dac9SGrant Likely  - rx-stash-idx : Denotes the index of the first byte from the received
59d524dac9SGrant Likely    buffer to stash in the L2.
60d524dac9SGrant Likely
61d524dac9SGrant LikelyExample:
62d524dac9SGrant Likely	ethernet@24000 {
63d524dac9SGrant Likely		device_type = "network";
64d524dac9SGrant Likely		model = "TSEC";
65d524dac9SGrant Likely		compatible = "gianfar";
66d524dac9SGrant Likely		reg = <0x24000 0x1000>;
67d524dac9SGrant Likely		local-mac-address = [ 00 E0 0C 00 73 00 ];
68d524dac9SGrant Likely		interrupts = <29 2 30 2 34 2>;
69d524dac9SGrant Likely		interrupt-parent = <&mpic>;
70d524dac9SGrant Likely		phy-handle = <&phy0>
71d524dac9SGrant Likely	};
72c78275f3SRichard Cochran
73c78275f3SRichard Cochran* Gianfar PTP clock nodes
74c78275f3SRichard Cochran
75c78275f3SRichard CochranGeneral Properties:
76c78275f3SRichard Cochran
77c78275f3SRichard Cochran  - compatible   Should be "fsl,etsec-ptp"
78c78275f3SRichard Cochran  - reg          Offset and length of the register set for the device
79c78275f3SRichard Cochran  - interrupts   There should be at least two interrupts. Some devices
80c78275f3SRichard Cochran                 have as many as four PTP related interrupts.
81c78275f3SRichard Cochran
82c78275f3SRichard CochranClock Properties:
83c78275f3SRichard Cochran
84e58f6f4fSAida Mynzhasova  - fsl,cksel        Timer reference clock source.
85c78275f3SRichard Cochran  - fsl,tclk-period  Timer reference clock period in nanoseconds.
86c78275f3SRichard Cochran  - fsl,tmr-prsc     Prescaler, divides the output clock.
87c78275f3SRichard Cochran  - fsl,tmr-add      Frequency compensation value.
88c78275f3SRichard Cochran  - fsl,tmr-fiper1   Fixed interval period pulse generator.
89c78275f3SRichard Cochran  - fsl,tmr-fiper2   Fixed interval period pulse generator.
90c78275f3SRichard Cochran  - fsl,max-adj      Maximum frequency adjustment in parts per billion.
91c78275f3SRichard Cochran
92c78275f3SRichard Cochran  These properties set the operational parameters for the PTP
93c78275f3SRichard Cochran  clock. You must choose these carefully for the clock to work right.
94c78275f3SRichard Cochran  Here is how to figure good values:
95c78275f3SRichard Cochran
96e58f6f4fSAida Mynzhasova  TimerOsc     = selected reference clock   MHz
97c78275f3SRichard Cochran  tclk_period  = desired clock period       nanoseconds
98c78275f3SRichard Cochran  NominalFreq  = 1000 / tclk_period         MHz
99c78275f3SRichard Cochran  FreqDivRatio = TimerOsc / NominalFreq     (must be greater that 1.0)
100c78275f3SRichard Cochran  tmr_add      = ceil(2^32 / FreqDivRatio)
101c78275f3SRichard Cochran  OutputClock  = NominalFreq / tmr_prsc     MHz
102c78275f3SRichard Cochran  PulseWidth   = 1 / OutputClock            microseconds
103c78275f3SRichard Cochran  FiperFreq1   = desired frequency in Hz
104c78275f3SRichard Cochran  FiperDiv1    = 1000000 * OutputClock / FiperFreq1
105c78275f3SRichard Cochran  tmr_fiper1   = tmr_prsc * tclk_period * FiperDiv1 - tclk_period
106c78275f3SRichard Cochran  max_adj      = 1000000000 * (FreqDivRatio - 1.0) - 1
107c78275f3SRichard Cochran
108c78275f3SRichard Cochran  The calculation for tmr_fiper2 is the same as for tmr_fiper1. The
109c78275f3SRichard Cochran  driver expects that tmr_fiper1 will be correctly set to produce a 1
110c78275f3SRichard Cochran  Pulse Per Second (PPS) signal, since this will be offered to the PPS
111c78275f3SRichard Cochran  subsystem to synchronize the Linux clock.
112c78275f3SRichard Cochran
113e58f6f4fSAida Mynzhasova  Reference clock source is determined by the value, which is holded
114e58f6f4fSAida Mynzhasova  in CKSEL bits in TMR_CTRL register. "fsl,cksel" property keeps the
115e58f6f4fSAida Mynzhasova  value, which will be directly written in those bits, that is why,
116e58f6f4fSAida Mynzhasova  according to reference manual, the next clock sources can be used:
117e58f6f4fSAida Mynzhasova
118e58f6f4fSAida Mynzhasova  <0> - external high precision timer reference clock (TSEC_TMR_CLK
119e58f6f4fSAida Mynzhasova        input is used for this purpose);
120e58f6f4fSAida Mynzhasova  <1> - eTSEC system clock;
121e58f6f4fSAida Mynzhasova  <2> - eTSEC1 transmit clock;
122e58f6f4fSAida Mynzhasova  <3> - RTC clock input.
123e58f6f4fSAida Mynzhasova
124e58f6f4fSAida Mynzhasova  When this attribute is not used, eTSEC system clock will serve as
125e58f6f4fSAida Mynzhasova  IEEE 1588 timer reference clock.
126e58f6f4fSAida Mynzhasova
127c78275f3SRichard CochranExample:
128c78275f3SRichard Cochran
129c78275f3SRichard Cochran	ptp_clock@24E00 {
130c78275f3SRichard Cochran		compatible = "fsl,etsec-ptp";
131c78275f3SRichard Cochran		reg = <0x24E00 0xB0>;
132c78275f3SRichard Cochran		interrupts = <12 0x8 13 0x8>;
133c78275f3SRichard Cochran		interrupt-parent = < &ipic >;
134e58f6f4fSAida Mynzhasova		fsl,cksel       = <1>;
135c78275f3SRichard Cochran		fsl,tclk-period = <10>;
136c78275f3SRichard Cochran		fsl,tmr-prsc    = <100>;
137c78275f3SRichard Cochran		fsl,tmr-add     = <0x999999A4>;
138c78275f3SRichard Cochran		fsl,tmr-fiper1  = <0x3B9AC9F6>;
139c78275f3SRichard Cochran		fsl,tmr-fiper2  = <0x00018696>;
140c78275f3SRichard Cochran		fsl,max-adj     = <659999998>;
141c78275f3SRichard Cochran	};
142