1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/net/fsl,fec.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Freescale Fast Ethernet Controller (FEC) 8 9maintainers: 10 - Joakim Zhang <qiangqing.zhang@nxp.com> 11 12allOf: 13 - $ref: ethernet-controller.yaml# 14 15properties: 16 compatible: 17 oneOf: 18 - enum: 19 - fsl,imx25-fec 20 - fsl,imx27-fec 21 - fsl,imx28-fec 22 - fsl,imx6q-fec 23 - fsl,mvf600-fec 24 - fsl,s32v234-fec 25 - items: 26 - enum: 27 - fsl,imx53-fec 28 - fsl,imx6sl-fec 29 - const: fsl,imx25-fec 30 - items: 31 - enum: 32 - fsl,imx35-fec 33 - fsl,imx51-fec 34 - const: fsl,imx27-fec 35 - items: 36 - enum: 37 - fsl,imx6ul-fec 38 - fsl,imx6sx-fec 39 - const: fsl,imx6q-fec 40 - items: 41 - enum: 42 - fsl,imx7d-fec 43 - const: fsl,imx6sx-fec 44 - items: 45 - const: fsl,imx8mq-fec 46 - const: fsl,imx6sx-fec 47 - items: 48 - enum: 49 - fsl,imx8mm-fec 50 - fsl,imx8mn-fec 51 - fsl,imx8mp-fec 52 - const: fsl,imx8mq-fec 53 - const: fsl,imx6sx-fec 54 - items: 55 - const: fsl,imx8qm-fec 56 - const: fsl,imx6sx-fec 57 - items: 58 - enum: 59 - fsl,imx8qxp-fec 60 - const: fsl,imx8qm-fec 61 - const: fsl,imx6sx-fec 62 - items: 63 - enum: 64 - fsl,imx8ulp-fec 65 - const: fsl,imx6ul-fec 66 - const: fsl,imx6q-fec 67 68 reg: 69 maxItems: 1 70 71 interrupts: 72 minItems: 1 73 maxItems: 4 74 75 interrupt-names: 76 oneOf: 77 - items: 78 - const: int0 79 - items: 80 - const: int0 81 - const: pps 82 - items: 83 - const: int0 84 - const: int1 85 - const: int2 86 - items: 87 - const: int0 88 - const: int1 89 - const: int2 90 - const: pps 91 92 clocks: 93 minItems: 2 94 maxItems: 5 95 description: 96 The "ipg", for MAC ipg_clk_s, ipg_clk_mac_s that are for register accessing. 97 The "ahb", for MAC ipg_clk, ipg_clk_mac that are bus clock. 98 The "ptp"(option), for IEEE1588 timer clock that requires the clock. 99 The "enet_clk_ref"(option), for MAC transmit/receiver reference clock like 100 RGMII TXC clock or RMII reference clock. It depends on board design, 101 the clock is required if RGMII TXC and RMII reference clock source from 102 SOC internal PLL. 103 The "enet_out"(option), output clock for external device, like supply clock 104 for PHY. The clock is required if PHY clock source from SOC. 105 The "enet_2x_txclk"(option), for RGMII sampling clock which fixed at 250Mhz. 106 The clock is required if SoC RGMII enable clock delay. 107 108 clock-names: 109 minItems: 2 110 maxItems: 5 111 items: 112 enum: 113 - ipg 114 - ahb 115 - ptp 116 - enet_clk_ref 117 - enet_out 118 - enet_2x_txclk 119 120 phy-mode: true 121 122 phy-handle: true 123 124 fixed-link: true 125 126 local-mac-address: true 127 128 mac-address: true 129 130 nvmem-cells: true 131 132 nvmem-cell-names: true 133 134 tx-internal-delay-ps: 135 enum: [0, 2000] 136 137 rx-internal-delay-ps: 138 enum: [0, 2000] 139 140 phy-supply: 141 description: 142 Regulator that powers the Ethernet PHY. 143 144 fsl,num-tx-queues: 145 $ref: /schemas/types.yaml#/definitions/uint32 146 description: 147 The property is valid for enet-avb IP, which supports hw multi queues. 148 Should specify the tx queue number, otherwise set tx queue number to 1. 149 enum: [1, 2, 3] 150 151 fsl,num-rx-queues: 152 $ref: /schemas/types.yaml#/definitions/uint32 153 description: 154 The property is valid for enet-avb IP, which supports hw multi queues. 155 Should specify the rx queue number, otherwise set rx queue number to 1. 156 enum: [1, 2, 3] 157 158 fsl,magic-packet: 159 $ref: /schemas/types.yaml#/definitions/flag 160 description: 161 If present, indicates that the hardware supports waking up via magic packet. 162 163 fsl,err006687-workaround-present: 164 $ref: /schemas/types.yaml#/definitions/flag 165 description: 166 If present indicates that the system has the hardware workaround for 167 ERR006687 applied and does not need a software workaround. 168 169 fsl,stop-mode: 170 $ref: /schemas/types.yaml#/definitions/phandle-array 171 items: 172 - items: 173 - description: phandle to general purpose register node 174 - description: the gpr register offset for ENET stop request 175 - description: the gpr bit offset for ENET stop request 176 description: 177 Register bits of stop mode control, the format is <&gpr req_gpr req_bit>. 178 179 mdio: 180 $ref: mdio.yaml# 181 unevaluatedProperties: false 182 description: 183 Specifies the mdio bus in the FEC, used as a container for phy nodes. 184 185 # Deprecated optional properties: 186 # To avoid these, create a phy node according to ethernet-phy.yaml in the same 187 # directory, and point the FEC's "phy-handle" property to it. Then use 188 # the phy's reset binding, again described by ethernet-phy.yaml. 189 190 phy-reset-gpios: 191 deprecated: true 192 description: 193 Should specify the gpio for phy reset. 194 195 phy-reset-duration: 196 $ref: /schemas/types.yaml#/definitions/uint32 197 deprecated: true 198 description: 199 Reset duration in milliseconds. Should present only if property 200 "phy-reset-gpios" is available. Missing the property will have the 201 duration be 1 millisecond. Numbers greater than 1000 are invalid 202 and 1 millisecond will be used instead. 203 204 phy-reset-active-high: 205 type: boolean 206 deprecated: true 207 description: 208 If present then the reset sequence using the GPIO specified in the 209 "phy-reset-gpios" property is reversed (H=reset state, L=operation state). 210 211 phy-reset-post-delay: 212 $ref: /schemas/types.yaml#/definitions/uint32 213 deprecated: true 214 description: 215 Post reset delay in milliseconds. If present then a delay of phy-reset-post-delay 216 milliseconds will be observed after the phy-reset-gpios has been toggled. 217 Can be omitted thus no delay is observed. Delay is in range of 1ms to 1000ms. 218 Other delays are invalid. 219 220required: 221 - compatible 222 - reg 223 - interrupts 224 225# FIXME: We had better set additionalProperties to false to avoid invalid or at 226# least undocumented properties. However, PHY may have a deprecated option to 227# place PHY OF properties in the MAC node, such as Micrel PHY, and we can find 228# these boards which is based on i.MX6QDL. 229unevaluatedProperties: false 230 231examples: 232 - | 233 ethernet@83fec000 { 234 compatible = "fsl,imx51-fec", "fsl,imx27-fec"; 235 reg = <0x83fec000 0x4000>; 236 interrupts = <87>; 237 phy-mode = "mii"; 238 phy-reset-gpios = <&gpio2 14 0>; 239 phy-supply = <®_fec_supply>; 240 }; 241 242 ethernet@83fed000 { 243 compatible = "fsl,imx51-fec", "fsl,imx27-fec"; 244 reg = <0x83fed000 0x4000>; 245 interrupts = <87>; 246 phy-mode = "mii"; 247 phy-reset-gpios = <&gpio2 14 0>; 248 phy-supply = <®_fec_supply>; 249 phy-handle = <ðphy0>; 250 251 mdio { 252 #address-cells = <1>; 253 #size-cells = <0>; 254 255 ethphy0: ethernet-phy@0 { 256 compatible = "ethernet-phy-ieee802.3-c22"; 257 reg = <0>; 258 }; 259 }; 260 }; 261