1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/net/fsl,fec.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Freescale Fast Ethernet Controller (FEC) 8 9maintainers: 10 - Shawn Guo <shawnguo@kernel.org> 11 - Wei Fang <wei.fang@nxp.com> 12 - NXP Linux Team <linux-imx@nxp.com> 13 14allOf: 15 - $ref: ethernet-controller.yaml# 16 17properties: 18 compatible: 19 oneOf: 20 - enum: 21 - fsl,imx25-fec 22 - fsl,imx27-fec 23 - fsl,imx28-fec 24 - fsl,imx6q-fec 25 - fsl,mvf600-fec 26 - fsl,s32v234-fec 27 - items: 28 - enum: 29 - fsl,imx53-fec 30 - fsl,imx6sl-fec 31 - const: fsl,imx25-fec 32 - items: 33 - enum: 34 - fsl,imx35-fec 35 - fsl,imx51-fec 36 - const: fsl,imx27-fec 37 - items: 38 - enum: 39 - fsl,imx6ul-fec 40 - fsl,imx6sx-fec 41 - const: fsl,imx6q-fec 42 - items: 43 - enum: 44 - fsl,imx7d-fec 45 - const: fsl,imx6sx-fec 46 - items: 47 - const: fsl,imx8mq-fec 48 - const: fsl,imx6sx-fec 49 - items: 50 - enum: 51 - fsl,imx8mm-fec 52 - fsl,imx8mn-fec 53 - fsl,imx8mp-fec 54 - fsl,imx93-fec 55 - const: fsl,imx8mq-fec 56 - const: fsl,imx6sx-fec 57 - items: 58 - const: fsl,imx8qm-fec 59 - const: fsl,imx6sx-fec 60 - items: 61 - enum: 62 - fsl,imx8qxp-fec 63 - const: fsl,imx8qm-fec 64 - const: fsl,imx6sx-fec 65 - items: 66 - enum: 67 - fsl,imx8ulp-fec 68 - const: fsl,imx6ul-fec 69 - const: fsl,imx6q-fec 70 71 reg: 72 maxItems: 1 73 74 interrupts: 75 minItems: 1 76 maxItems: 4 77 78 interrupt-names: 79 oneOf: 80 - items: 81 - const: int0 82 - items: 83 - const: int0 84 - const: pps 85 - items: 86 - const: int0 87 - const: int1 88 - const: int2 89 - items: 90 - const: int0 91 - const: int1 92 - const: int2 93 - const: pps 94 95 clocks: 96 minItems: 2 97 maxItems: 5 98 description: 99 The "ipg", for MAC ipg_clk_s, ipg_clk_mac_s that are for register accessing. 100 The "ahb", for MAC ipg_clk, ipg_clk_mac that are bus clock. 101 The "ptp"(option), for IEEE1588 timer clock that requires the clock. 102 The "enet_clk_ref"(option), for MAC transmit/receiver reference clock like 103 RGMII TXC clock or RMII reference clock. It depends on board design, 104 the clock is required if RGMII TXC and RMII reference clock source from 105 SOC internal PLL. 106 The "enet_out"(option), output clock for external device, like supply clock 107 for PHY. The clock is required if PHY clock source from SOC. 108 The "enet_2x_txclk"(option), for RGMII sampling clock which fixed at 250Mhz. 109 The clock is required if SoC RGMII enable clock delay. 110 111 clock-names: 112 minItems: 2 113 maxItems: 5 114 items: 115 enum: 116 - ipg 117 - ahb 118 - ptp 119 - enet_clk_ref 120 - enet_out 121 - enet_2x_txclk 122 123 phy-mode: true 124 125 phy-handle: true 126 127 fixed-link: true 128 129 local-mac-address: true 130 131 mac-address: true 132 133 nvmem-cells: true 134 135 nvmem-cell-names: true 136 137 tx-internal-delay-ps: 138 enum: [0, 2000] 139 140 rx-internal-delay-ps: 141 enum: [0, 2000] 142 143 phy-supply: 144 description: 145 Regulator that powers the Ethernet PHY. 146 147 fsl,num-tx-queues: 148 $ref: /schemas/types.yaml#/definitions/uint32 149 description: 150 The property is valid for enet-avb IP, which supports hw multi queues. 151 Should specify the tx queue number, otherwise set tx queue number to 1. 152 enum: [1, 2, 3] 153 154 fsl,num-rx-queues: 155 $ref: /schemas/types.yaml#/definitions/uint32 156 description: 157 The property is valid for enet-avb IP, which supports hw multi queues. 158 Should specify the rx queue number, otherwise set rx queue number to 1. 159 enum: [1, 2, 3] 160 161 fsl,magic-packet: 162 $ref: /schemas/types.yaml#/definitions/flag 163 description: 164 If present, indicates that the hardware supports waking up via magic packet. 165 166 fsl,err006687-workaround-present: 167 $ref: /schemas/types.yaml#/definitions/flag 168 description: 169 If present indicates that the system has the hardware workaround for 170 ERR006687 applied and does not need a software workaround. 171 172 fsl,stop-mode: 173 $ref: /schemas/types.yaml#/definitions/phandle-array 174 items: 175 - items: 176 - description: phandle to general purpose register node 177 - description: the gpr register offset for ENET stop request 178 - description: the gpr bit offset for ENET stop request 179 description: 180 Register bits of stop mode control, the format is <&gpr req_gpr req_bit>. 181 182 mdio: 183 $ref: mdio.yaml# 184 unevaluatedProperties: false 185 description: 186 Specifies the mdio bus in the FEC, used as a container for phy nodes. 187 188 # Deprecated optional properties: 189 # To avoid these, create a phy node according to ethernet-phy.yaml in the same 190 # directory, and point the FEC's "phy-handle" property to it. Then use 191 # the phy's reset binding, again described by ethernet-phy.yaml. 192 193 phy-reset-gpios: 194 deprecated: true 195 description: 196 Should specify the gpio for phy reset. 197 198 phy-reset-duration: 199 $ref: /schemas/types.yaml#/definitions/uint32 200 deprecated: true 201 description: 202 Reset duration in milliseconds. Should present only if property 203 "phy-reset-gpios" is available. Missing the property will have the 204 duration be 1 millisecond. Numbers greater than 1000 are invalid 205 and 1 millisecond will be used instead. 206 207 phy-reset-active-high: 208 type: boolean 209 deprecated: true 210 description: 211 If present then the reset sequence using the GPIO specified in the 212 "phy-reset-gpios" property is reversed (H=reset state, L=operation state). 213 214 phy-reset-post-delay: 215 $ref: /schemas/types.yaml#/definitions/uint32 216 deprecated: true 217 description: 218 Post reset delay in milliseconds. If present then a delay of phy-reset-post-delay 219 milliseconds will be observed after the phy-reset-gpios has been toggled. 220 Can be omitted thus no delay is observed. Delay is in range of 1ms to 1000ms. 221 Other delays are invalid. 222 223required: 224 - compatible 225 - reg 226 - interrupts 227 228# FIXME: We had better set additionalProperties to false to avoid invalid or at 229# least undocumented properties. However, PHY may have a deprecated option to 230# place PHY OF properties in the MAC node, such as Micrel PHY, and we can find 231# these boards which is based on i.MX6QDL. 232unevaluatedProperties: false 233 234examples: 235 - | 236 ethernet@83fec000 { 237 compatible = "fsl,imx51-fec", "fsl,imx27-fec"; 238 reg = <0x83fec000 0x4000>; 239 interrupts = <87>; 240 phy-mode = "mii"; 241 phy-reset-gpios = <&gpio2 14 0>; 242 phy-supply = <®_fec_supply>; 243 }; 244 245 ethernet@83fed000 { 246 compatible = "fsl,imx51-fec", "fsl,imx27-fec"; 247 reg = <0x83fed000 0x4000>; 248 interrupts = <87>; 249 phy-mode = "mii"; 250 phy-reset-gpios = <&gpio2 14 0>; 251 phy-supply = <®_fec_supply>; 252 phy-handle = <ðphy0>; 253 254 mdio { 255 #address-cells = <1>; 256 #size-cells = <0>; 257 258 ethphy0: ethernet-phy@0 { 259 compatible = "ethernet-phy-ieee802.3-c22"; 260 reg = <0>; 261 }; 262 }; 263 }; 264