1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/net/ethernet-controller.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Ethernet Controller Generic Binding 8 9maintainers: 10 - David S. Miller <davem@davemloft.net> 11 12properties: 13 $nodename: 14 pattern: "^ethernet(@.*)?$" 15 16 label: 17 $ref: /schemas/types.yaml#/definitions/string 18 description: Human readable label on a port of a box. 19 20 local-mac-address: 21 description: 22 Specifies the MAC address that was assigned to the network device. 23 $ref: /schemas/types.yaml#/definitions/uint8-array 24 minItems: 6 25 maxItems: 6 26 27 mac-address: 28 description: 29 Specifies the MAC address that was last used by the boot 30 program; should be used in cases where the MAC address assigned 31 to the device by the boot program is different from the 32 local-mac-address property. 33 $ref: /schemas/types.yaml#/definitions/uint8-array 34 minItems: 6 35 maxItems: 6 36 37 max-frame-size: 38 $ref: /schemas/types.yaml#/definitions/uint32 39 description: 40 Maximum transfer unit (IEEE defined MTU), rather than the 41 maximum frame size (there\'s contradiction in the Devicetree 42 Specification). 43 44 max-speed: 45 $ref: /schemas/types.yaml#/definitions/uint32 46 description: 47 Specifies maximum speed in Mbit/s supported by the device. 48 49 nvmem-cells: 50 maxItems: 1 51 description: 52 Reference to an nvmem node for the MAC address 53 54 nvmem-cell-names: 55 const: mac-address 56 57 phy-connection-type: 58 description: 59 Specifies interface type between the Ethernet device and a physical 60 layer (PHY) device. 61 enum: 62 # There is not a standard bus between the MAC and the PHY, 63 # something proprietary is being used to embed the PHY in the 64 # MAC. 65 - internal 66 - mii 67 - gmii 68 - sgmii 69 - qsgmii 70 - tbi 71 - rev-mii 72 - rmii 73 - rev-rmii 74 - moca 75 76 # RX and TX delays are added by the MAC when required 77 - rgmii 78 79 # RGMII with internal RX and TX delays provided by the PHY, 80 # the MAC should not add the RX or TX delays in this case 81 - rgmii-id 82 83 # RGMII with internal RX delay provided by the PHY, the MAC 84 # should not add an RX delay in this case 85 - rgmii-rxid 86 87 # RGMII with internal TX delay provided by the PHY, the MAC 88 # should not add an TX delay in this case 89 - rgmii-txid 90 - rtbi 91 - smii 92 - xgmii 93 - trgmii 94 - 1000base-x 95 - 2500base-x 96 - 5gbase-r 97 - rxaui 98 - xaui 99 100 # 10GBASE-KR, XFI, SFI 101 - 10gbase-kr 102 - usxgmii 103 - 10gbase-r 104 - 25gbase-r 105 106 phy-mode: 107 $ref: "#/properties/phy-connection-type" 108 109 pcs-handle: 110 $ref: /schemas/types.yaml#/definitions/phandle 111 description: 112 Specifies a reference to a node representing a PCS PHY device on a MDIO 113 bus to link with an external PHY (phy-handle) if exists. 114 115 phy-handle: 116 $ref: /schemas/types.yaml#/definitions/phandle 117 description: 118 Specifies a reference to a node representing a PHY device. 119 120 phy: 121 $ref: "#/properties/phy-handle" 122 deprecated: true 123 124 phy-device: 125 $ref: "#/properties/phy-handle" 126 deprecated: true 127 128 rx-fifo-depth: 129 $ref: /schemas/types.yaml#/definitions/uint32 130 description: 131 The size of the controller\'s receive fifo in bytes. This is used 132 for components that can have configurable receive fifo sizes, 133 and is useful for determining certain configuration settings 134 such as flow control thresholds. 135 136 rx-internal-delay-ps: 137 description: | 138 RGMII Receive Clock Delay defined in pico seconds. 139 This is used for controllers that have configurable RX internal delays. 140 If this property is present then the MAC applies the RX delay. 141 142 sfp: 143 $ref: /schemas/types.yaml#/definitions/phandle 144 description: 145 Specifies a reference to a node representing a SFP cage. 146 147 tx-fifo-depth: 148 $ref: /schemas/types.yaml#/definitions/uint32 149 description: 150 The size of the controller\'s transmit fifo in bytes. This 151 is used for components that can have configurable fifo sizes. 152 153 tx-internal-delay-ps: 154 description: | 155 RGMII Transmit Clock Delay defined in pico seconds. 156 This is used for controllers that have configurable TX internal delays. 157 If this property is present then the MAC applies the TX delay. 158 159 managed: 160 description: 161 Specifies the PHY management type. If auto is set and fixed-link 162 is not specified, it uses MDIO for management. 163 $ref: /schemas/types.yaml#/definitions/string 164 default: auto 165 enum: 166 - auto 167 - in-band-status 168 169 fixed-link: 170 oneOf: 171 - $ref: /schemas/types.yaml#/definitions/uint32-array 172 deprecated: true 173 items: 174 - minimum: 0 175 maximum: 31 176 description: 177 Emulated PHY ID, choose any but unique to the all 178 specified fixed-links 179 180 - enum: [0, 1] 181 description: 182 Duplex configuration. 0 for half duplex or 1 for 183 full duplex 184 185 - enum: [10, 100, 1000, 2500, 10000] 186 description: 187 Link speed in Mbits/sec. 188 189 - enum: [0, 1] 190 description: 191 Pause configuration. 0 for no pause, 1 for pause 192 193 - enum: [0, 1] 194 description: 195 Asymmetric pause configuration. 0 for no asymmetric 196 pause, 1 for asymmetric pause 197 - type: object 198 additionalProperties: false 199 properties: 200 speed: 201 description: 202 Link speed. 203 $ref: /schemas/types.yaml#/definitions/uint32 204 enum: [10, 100, 1000, 2500, 10000] 205 206 full-duplex: 207 $ref: /schemas/types.yaml#/definitions/flag 208 description: 209 Indicates that full-duplex is used. When absent, half 210 duplex is assumed. 211 212 pause: 213 $ref: /schemas/types.yaml#definitions/flag 214 description: 215 Indicates that pause should be enabled. 216 217 asym-pause: 218 $ref: /schemas/types.yaml#/definitions/flag 219 description: 220 Indicates that asym_pause should be enabled. 221 222 link-gpios: 223 maxItems: 1 224 description: 225 GPIO to determine if the link is up 226 227 required: 228 - speed 229 230additionalProperties: true 231 232... 233