1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/dsa/renesas,rzn1-a5psw.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Renesas RZ/N1 Advanced 5 ports ethernet switch
8
9maintainers:
10  - Clément Léger <clement.leger@bootlin.com>
11
12description: |
13  The advanced 5 ports switch is present on the Renesas RZ/N1 SoC family and
14  handles 4 ports + 1 CPU management port.
15
16allOf:
17  - $ref: dsa.yaml#
18
19properties:
20  compatible:
21    items:
22      - enum:
23          - renesas,r9a06g032-a5psw
24      - const: renesas,rzn1-a5psw
25
26  reg:
27    maxItems: 1
28
29  power-domains:
30    maxItems: 1
31
32  mdio:
33    $ref: /schemas/net/mdio.yaml#
34    unevaluatedProperties: false
35
36  clocks:
37    items:
38      - description: AHB clock used for the switch register interface
39      - description: Switch system clock
40
41  clock-names:
42    items:
43      - const: hclk
44      - const: clk
45
46  ethernet-ports:
47    type: object
48    properties:
49      '#address-cells':
50        const: 1
51      '#size-cells':
52        const: 0
53
54    patternProperties:
55      "^(ethernet-)?port@[0-4]$":
56        type: object
57        description: Ethernet switch ports
58
59        properties:
60          pcs-handle:
61            description:
62              phandle pointing to a PCS sub-node compatible with
63              renesas,rzn1-miic.yaml#
64            $ref: /schemas/types.yaml#/definitions/phandle
65
66unevaluatedProperties: false
67
68required:
69  - compatible
70  - reg
71  - clocks
72  - clock-names
73  - power-domains
74
75examples:
76  - |
77    #include <dt-bindings/gpio/gpio.h>
78    #include <dt-bindings/clock/r9a06g032-sysctrl.h>
79
80    switch@44050000 {
81        compatible = "renesas,r9a06g032-a5psw", "renesas,rzn1-a5psw";
82        reg = <0x44050000 0x10000>;
83        clocks = <&sysctrl R9A06G032_HCLK_SWITCH>, <&sysctrl R9A06G032_CLK_SWITCH>;
84        clock-names = "hclk", "clk";
85        power-domains = <&sysctrl>;
86
87        dsa,member = <0 0>;
88
89        ethernet-ports {
90            #address-cells = <1>;
91            #size-cells = <0>;
92
93            port@0 {
94                reg = <0>;
95                label = "lan0";
96                phy-handle = <&switch0phy3>;
97                pcs-handle = <&mii_conv4>;
98            };
99
100            port@1 {
101                reg = <1>;
102                label = "lan1";
103                phy-handle = <&switch0phy1>;
104                pcs-handle = <&mii_conv3>;
105            };
106
107            port@4 {
108                reg = <4>;
109                ethernet = <&gmac2>;
110                label = "cpu";
111                fixed-link {
112                  speed = <1000>;
113                  full-duplex;
114                };
115            };
116        };
117
118        mdio {
119            #address-cells = <1>;
120            #size-cells = <0>;
121
122            reset-gpios = <&gpio0a 2 GPIO_ACTIVE_HIGH>;
123            reset-delay-us = <15>;
124            clock-frequency = <2500000>;
125
126            switch0phy1: ethernet-phy@1{
127                reg = <1>;
128            };
129
130            switch0phy3: ethernet-phy@3{
131                reg = <3>;
132            };
133        };
134    };
135