1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/net/dsa/realtek.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Realtek switches for unmanaged switches 8 9allOf: 10 - $ref: dsa.yaml# 11 12maintainers: 13 - Linus Walleij <linus.walleij@linaro.org> 14 15description: 16 Realtek advertises these chips as fast/gigabit switches or unmanaged 17 switches. They can be controlled using different interfaces, like SMI, 18 MDIO or SPI. 19 20 The SMI "Simple Management Interface" is a two-wire protocol using 21 bit-banged GPIO that while it reuses the MDIO lines MCK and MDIO does 22 not use the MDIO protocol. This binding defines how to specify the 23 SMI-based Realtek devices. The realtek-smi driver is a platform driver 24 and it must be inserted inside a platform node. 25 26 The MDIO-connected switches use MDIO protocol to access their registers. 27 The realtek-mdio driver is an MDIO driver and it must be inserted inside 28 an MDIO node. 29 30properties: 31 compatible: 32 enum: 33 - realtek,rtl8365mb 34 - realtek,rtl8366 35 - realtek,rtl8366rb 36 - realtek,rtl8366s 37 - realtek,rtl8367 38 - realtek,rtl8367b 39 - realtek,rtl8367rb 40 - realtek,rtl8367s 41 - realtek,rtl8368s 42 - realtek,rtl8369 43 - realtek,rtl8370 44 description: | 45 realtek,rtl8365mb: 4+1 ports 46 realtek,rtl8366: 5+1 ports 47 realtek,rtl8366rb: 5+1 ports 48 realtek,rtl8366s: 5+1 ports 49 realtek,rtl8367: 50 realtek,rtl8367b: 51 realtek,rtl8367rb: 5+2 ports 52 realtek,rtl8367s: 5+2 ports 53 realtek,rtl8368s: 8 ports 54 realtek,rtl8369: 8+1 ports 55 realtek,rtl8370: 8+2 ports 56 57 mdc-gpios: 58 description: GPIO line for the MDC clock line. 59 maxItems: 1 60 61 mdio-gpios: 62 description: GPIO line for the MDIO data line. 63 maxItems: 1 64 65 reset-gpios: 66 description: GPIO to be used to reset the whole device 67 maxItems: 1 68 69 realtek,disable-leds: 70 type: boolean 71 description: | 72 if the LED drivers are not used in the hardware design, 73 this will disable them so they are not turned on 74 and wasting power. 75 76 interrupt-controller: 77 type: object 78 description: | 79 This defines an interrupt controller with an IRQ line (typically 80 a GPIO) that will demultiplex and handle the interrupt from the single 81 interrupt line coming out of one of the Realtek switch chips. It most 82 importantly provides link up/down interrupts to the PHY blocks inside 83 the ASIC. 84 85 properties: 86 87 interrupt-controller: true 88 89 interrupts: 90 maxItems: 1 91 description: 92 A single IRQ line from the switch, either active LOW or HIGH 93 94 '#address-cells': 95 const: 0 96 97 '#interrupt-cells': 98 const: 1 99 100 required: 101 - interrupt-controller 102 - '#address-cells' 103 - '#interrupt-cells' 104 105 mdio: 106 $ref: /schemas/net/mdio.yaml# 107 unevaluatedProperties: false 108 109 properties: 110 compatible: 111 const: realtek,smi-mdio 112 113if: 114 required: 115 - reg 116 117then: 118 not: 119 required: 120 - mdc-gpios 121 - mdio-gpios 122 - mdio 123 124 properties: 125 mdc-gpios: false 126 mdio-gpios: false 127 mdio: false 128 129else: 130 required: 131 - mdc-gpios 132 - mdio-gpios 133 - mdio 134 - reset-gpios 135 136required: 137 - compatible 138 139 # - mdc-gpios 140 # - mdio-gpios 141 # - reset-gpios 142 # - mdio 143 144unevaluatedProperties: false 145 146examples: 147 - | 148 #include <dt-bindings/gpio/gpio.h> 149 #include <dt-bindings/interrupt-controller/irq.h> 150 151 platform { 152 switch { 153 compatible = "realtek,rtl8366rb"; 154 /* 22 = MDIO (has input reads), 21 = MDC (clock, output only) */ 155 mdc-gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>; 156 mdio-gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>; 157 reset-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; 158 159 switch_intc1: interrupt-controller { 160 /* GPIO 15 provides the interrupt */ 161 interrupt-parent = <&gpio0>; 162 interrupts = <15 IRQ_TYPE_LEVEL_LOW>; 163 interrupt-controller; 164 #address-cells = <0>; 165 #interrupt-cells = <1>; 166 }; 167 168 ports { 169 #address-cells = <1>; 170 #size-cells = <0>; 171 port@0 { 172 reg = <0>; 173 label = "lan0"; 174 phy-handle = <&phy0>; 175 }; 176 port@1 { 177 reg = <1>; 178 label = "lan1"; 179 phy-handle = <&phy1>; 180 }; 181 port@2 { 182 reg = <2>; 183 label = "lan2"; 184 phy-handle = <&phy2>; 185 }; 186 port@3 { 187 reg = <3>; 188 label = "lan3"; 189 phy-handle = <&phy3>; 190 }; 191 port@4 { 192 reg = <4>; 193 label = "wan"; 194 phy-handle = <&phy4>; 195 }; 196 port@5 { 197 reg = <5>; 198 label = "cpu"; 199 ethernet = <&gmac0>; 200 phy-mode = "rgmii"; 201 fixed-link { 202 speed = <1000>; 203 full-duplex; 204 }; 205 }; 206 }; 207 208 mdio { 209 compatible = "realtek,smi-mdio"; 210 #address-cells = <1>; 211 #size-cells = <0>; 212 213 phy0: ethernet-phy@0 { 214 reg = <0>; 215 interrupt-parent = <&switch_intc1>; 216 interrupts = <0>; 217 }; 218 phy1: ethernet-phy@1 { 219 reg = <1>; 220 interrupt-parent = <&switch_intc1>; 221 interrupts = <1>; 222 }; 223 phy2: ethernet-phy@2 { 224 reg = <2>; 225 interrupt-parent = <&switch_intc1>; 226 interrupts = <2>; 227 }; 228 phy3: ethernet-phy@3 { 229 reg = <3>; 230 interrupt-parent = <&switch_intc1>; 231 interrupts = <3>; 232 }; 233 phy4: ethernet-phy@4 { 234 reg = <4>; 235 interrupt-parent = <&switch_intc1>; 236 interrupts = <12>; 237 }; 238 }; 239 }; 240 }; 241 242 - | 243 #include <dt-bindings/gpio/gpio.h> 244 #include <dt-bindings/interrupt-controller/irq.h> 245 246 platform { 247 switch { 248 compatible = "realtek,rtl8365mb"; 249 mdc-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; 250 mdio-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; 251 reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; 252 253 switch_intc2: interrupt-controller { 254 interrupt-parent = <&gpio5>; 255 interrupts = <1 IRQ_TYPE_LEVEL_LOW>; 256 interrupt-controller; 257 #address-cells = <0>; 258 #interrupt-cells = <1>; 259 }; 260 261 ports { 262 #address-cells = <1>; 263 #size-cells = <0>; 264 port@0 { 265 reg = <0>; 266 label = "swp0"; 267 phy-handle = <ðphy0>; 268 }; 269 port@1 { 270 reg = <1>; 271 label = "swp1"; 272 phy-handle = <ðphy1>; 273 }; 274 port@2 { 275 reg = <2>; 276 label = "swp2"; 277 phy-handle = <ðphy2>; 278 }; 279 port@3 { 280 reg = <3>; 281 label = "swp3"; 282 phy-handle = <ðphy3>; 283 }; 284 port@6 { 285 reg = <6>; 286 label = "cpu"; 287 ethernet = <&fec1>; 288 phy-mode = "rgmii"; 289 tx-internal-delay-ps = <2000>; 290 rx-internal-delay-ps = <2000>; 291 292 fixed-link { 293 speed = <1000>; 294 full-duplex; 295 pause; 296 }; 297 }; 298 }; 299 300 mdio { 301 compatible = "realtek,smi-mdio"; 302 #address-cells = <1>; 303 #size-cells = <0>; 304 305 ethphy0: ethernet-phy@0 { 306 reg = <0>; 307 interrupt-parent = <&switch_intc2>; 308 interrupts = <0>; 309 }; 310 ethphy1: ethernet-phy@1 { 311 reg = <1>; 312 interrupt-parent = <&switch_intc2>; 313 interrupts = <1>; 314 }; 315 ethphy2: ethernet-phy@2 { 316 reg = <2>; 317 interrupt-parent = <&switch_intc2>; 318 interrupts = <2>; 319 }; 320 ethphy3: ethernet-phy@3 { 321 reg = <3>; 322 interrupt-parent = <&switch_intc2>; 323 interrupts = <3>; 324 }; 325 }; 326 }; 327 }; 328 329 - | 330 #include <dt-bindings/gpio/gpio.h> 331 #include <dt-bindings/interrupt-controller/irq.h> 332 333 mdio { 334 #address-cells = <1>; 335 #size-cells = <0>; 336 337 switch@29 { 338 compatible = "realtek,rtl8367s"; 339 reg = <29>; 340 341 reset-gpios = <&gpio2 20 GPIO_ACTIVE_LOW>; 342 343 switch_intc3: interrupt-controller { 344 interrupt-parent = <&gpio0>; 345 interrupts = <11 IRQ_TYPE_EDGE_FALLING>; 346 interrupt-controller; 347 #address-cells = <0>; 348 #interrupt-cells = <1>; 349 }; 350 351 ports { 352 #address-cells = <1>; 353 #size-cells = <0>; 354 355 port@0 { 356 reg = <0>; 357 label = "lan4"; 358 }; 359 360 port@1 { 361 reg = <1>; 362 label = "lan3"; 363 }; 364 365 port@2 { 366 reg = <2>; 367 label = "lan2"; 368 }; 369 370 port@3 { 371 reg = <3>; 372 label = "lan1"; 373 }; 374 375 port@4 { 376 reg = <4>; 377 label = "wan"; 378 }; 379 380 port@7 { 381 reg = <7>; 382 ethernet = <ðernet>; 383 phy-mode = "rgmii"; 384 tx-internal-delay-ps = <2000>; 385 rx-internal-delay-ps = <0>; 386 387 fixed-link { 388 speed = <1000>; 389 full-duplex; 390 }; 391 }; 392 }; 393 }; 394 }; 395