1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/dsa/qca8k.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Atheros QCA83xx switch family
8
9maintainers:
10  - John Crispin <john@phrozen.org>
11
12description:
13  If the QCA8K switch is connect to an SoC's external mdio-bus, each subnode
14  describing a port needs to have a valid phandle referencing the internal PHY
15  it is connected to. This is because there is no N:N mapping of port and PHY
16  ID. To declare the internal mdio-bus configuration, declare an MDIO node in
17  the switch node and declare the phandle for the port, referencing the internal
18  PHY it is connected to. In this config, an internal mdio-bus is registered and
19  the MDIO master is used for communication. Mixed external and internal
20  mdio-bus configurations are not supported by the hardware.
21
22properties:
23  compatible:
24    oneOf:
25      - enum:
26          - qca,qca8327
27          - qca,qca8328
28          - qca,qca8334
29          - qca,qca8337
30    description: |
31      qca,qca8328: referenced as AR8328(N)-AK1(A/B) QFN 176 pin package
32      qca,qca8327: referenced as AR8327(N)-AL1A DR-QFN 148 pin package
33      qca,qca8334: referenced as QCA8334-AL3C QFN 88 pin package
34      qca,qca8337: referenced as QCA8337N-AL3(B/C) DR-QFN 148 pin package
35
36  reg:
37    maxItems: 1
38
39  reset-gpios:
40    description:
41      GPIO to be used to reset the whole device
42    maxItems: 1
43
44  qca,ignore-power-on-sel:
45    $ref: /schemas/types.yaml#/definitions/flag
46    description:
47      Ignore power-on pin strapping to configure LED open-drain or EEPROM
48      presence. This is needed for devices with incorrect configuration or when
49      the OEM has decided not to use pin strapping and falls back to SW regs.
50
51  qca,led-open-drain:
52    $ref: /schemas/types.yaml#/definitions/flag
53    description:
54      Set LEDs to open-drain mode. This requires the qca,ignore-power-on-sel to
55      be set, otherwise the driver will fail at probe. This is required if the
56      OEM does not use pin strapping to set this mode and prefers to set it
57      using SW regs. The pin strappings related to LED open-drain mode are
58      B68 on the QCA832x and B49 on the QCA833x.
59
60  mdio:
61    $ref: /schemas/net/mdio.yaml#
62    unevaluatedProperties: false
63    description: Qca8k switch have an internal mdio to access switch port.
64                 If this is not present, the legacy mapping is used and the
65                 internal mdio access is used.
66                 With the legacy mapping the reg corresponding to the internal
67                 mdio is the switch reg with an offset of -1.
68
69$ref: "dsa.yaml#"
70
71patternProperties:
72  "^(ethernet-)?ports$":
73    type: object
74    patternProperties:
75      "^(ethernet-)?port@[0-6]$":
76        type: object
77        description: Ethernet switch ports
78
79        $ref: dsa-port.yaml#
80
81        properties:
82          qca,sgmii-rxclk-falling-edge:
83            $ref: /schemas/types.yaml#/definitions/flag
84            description:
85              Set the receive clock phase to falling edge. Mostly commonly used on
86              the QCA8327 with CPU port 0 set to SGMII.
87
88          qca,sgmii-txclk-falling-edge:
89            $ref: /schemas/types.yaml#/definitions/flag
90            description:
91              Set the transmit clock phase to falling edge.
92
93          qca,sgmii-enable-pll:
94            $ref: /schemas/types.yaml#/definitions/flag
95            description:
96              For SGMII CPU port, explicitly enable PLL, TX and RX chain along with
97              Signal Detection. On the QCA8327 this should not be enabled, otherwise
98              the SGMII port will not initialize. When used on the QCA8337, revision 3
99              or greater, a warning will be displayed. When the CPU port is set to
100              SGMII on the QCA8337, it is advised to set this unless a communication
101              issue is observed.
102
103        unevaluatedProperties: false
104
105oneOf:
106  - required:
107      - ports
108  - required:
109      - ethernet-ports
110
111required:
112  - compatible
113  - reg
114
115unevaluatedProperties: false
116
117examples:
118  - |
119    #include <dt-bindings/gpio/gpio.h>
120
121    mdio {
122        #address-cells = <1>;
123        #size-cells = <0>;
124
125        external_phy_port1: ethernet-phy@0 {
126            reg = <0>;
127        };
128
129        external_phy_port2: ethernet-phy@1 {
130            reg = <1>;
131        };
132
133        external_phy_port3: ethernet-phy@2 {
134            reg = <2>;
135        };
136
137        external_phy_port4: ethernet-phy@3 {
138            reg = <3>;
139        };
140
141        external_phy_port5: ethernet-phy@4 {
142            reg = <4>;
143        };
144
145        switch@10 {
146            compatible = "qca,qca8337";
147            reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
148            reg = <0x10>;
149
150            ports {
151                #address-cells = <1>;
152                #size-cells = <0>;
153
154                port@0 {
155                    reg = <0>;
156                    ethernet = <&gmac1>;
157                    phy-mode = "rgmii";
158
159                    fixed-link {
160                        speed = <1000>;
161                        full-duplex;
162                    };
163                };
164
165                port@1 {
166                    reg = <1>;
167                    label = "lan1";
168                    phy-handle = <&external_phy_port1>;
169                };
170
171                port@2 {
172                    reg = <2>;
173                    label = "lan2";
174                    phy-handle = <&external_phy_port2>;
175                };
176
177                port@3 {
178                    reg = <3>;
179                    label = "lan3";
180                    phy-handle = <&external_phy_port3>;
181                };
182
183                port@4 {
184                    reg = <4>;
185                    label = "lan4";
186                    phy-handle = <&external_phy_port4>;
187                };
188
189                port@5 {
190                    reg = <5>;
191                    label = "wan";
192                    phy-handle = <&external_phy_port5>;
193                };
194            };
195        };
196    };
197  - |
198    #include <dt-bindings/gpio/gpio.h>
199
200    mdio {
201        #address-cells = <1>;
202        #size-cells = <0>;
203
204        switch@10 {
205            compatible = "qca,qca8337";
206            reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
207            reg = <0x10>;
208
209            ports {
210                #address-cells = <1>;
211                #size-cells = <0>;
212
213                port@0 {
214                    reg = <0>;
215                    ethernet = <&gmac1>;
216                    phy-mode = "rgmii";
217
218                    fixed-link {
219                        speed = <1000>;
220                        full-duplex;
221                    };
222                };
223
224                port@1 {
225                    reg = <1>;
226                    label = "lan1";
227                    phy-mode = "internal";
228                    phy-handle = <&internal_phy_port1>;
229                };
230
231                port@2 {
232                    reg = <2>;
233                    label = "lan2";
234                    phy-mode = "internal";
235                    phy-handle = <&internal_phy_port2>;
236                };
237
238                port@3 {
239                    reg = <3>;
240                    label = "lan3";
241                    phy-mode = "internal";
242                    phy-handle = <&internal_phy_port3>;
243                };
244
245                port@4 {
246                    reg = <4>;
247                    label = "lan4";
248                    phy-mode = "internal";
249                    phy-handle = <&internal_phy_port4>;
250                };
251
252                port@5 {
253                    reg = <5>;
254                    label = "wan";
255                    phy-mode = "internal";
256                    phy-handle = <&internal_phy_port5>;
257                };
258
259                port@6 {
260                    reg = <0>;
261                    ethernet = <&gmac1>;
262                    phy-mode = "sgmii";
263
264                    qca,sgmii-rxclk-falling-edge;
265
266                    fixed-link {
267                        speed = <1000>;
268                        full-duplex;
269                    };
270                };
271            };
272
273            mdio {
274                #address-cells = <1>;
275                #size-cells = <0>;
276
277                internal_phy_port1: ethernet-phy@0 {
278                    reg = <0>;
279                };
280
281                internal_phy_port2: ethernet-phy@1 {
282                    reg = <1>;
283                };
284
285                internal_phy_port3: ethernet-phy@2 {
286                    reg = <2>;
287                };
288
289                internal_phy_port4: ethernet-phy@3 {
290                    reg = <3>;
291                };
292
293                internal_phy_port5: ethernet-phy@4 {
294                    reg = <4>;
295                };
296            };
297        };
298    };
299