1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/dsa/qca8k.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Atheros QCA83xx switch family
8
9maintainers:
10  - John Crispin <john@phrozen.org>
11
12description:
13  If the QCA8K switch is connect to an SoC's external mdio-bus, each subnode
14  describing a port needs to have a valid phandle referencing the internal PHY
15  it is connected to. This is because there is no N:N mapping of port and PHY
16  ID. To declare the internal mdio-bus configuration, declare an MDIO node in
17  the switch node and declare the phandle for the port, referencing the internal
18  PHY it is connected to. In this config, an internal mdio-bus is registered and
19  the MDIO master is used for communication. Mixed external and internal
20  mdio-bus configurations are not supported by the hardware.
21
22properties:
23  compatible:
24    oneOf:
25      - enum:
26          - qca,qca8327
27          - qca,qca8328
28          - qca,qca8334
29          - qca,qca8337
30    description: |
31      qca,qca8328: referenced as AR8328(N)-AK1(A/B) QFN 176 pin package
32      qca,qca8327: referenced as AR8327(N)-AL1A DR-QFN 148 pin package
33      qca,qca8334: referenced as QCA8334-AL3C QFN 88 pin package
34      qca,qca8337: referenced as QCA8337N-AL3(B/C) DR-QFN 148 pin package
35
36  reg:
37    maxItems: 1
38
39  reset-gpios:
40    description:
41      GPIO to be used to reset the whole device
42    maxItems: 1
43
44  qca,ignore-power-on-sel:
45    $ref: /schemas/types.yaml#/definitions/flag
46    description:
47      Ignore power-on pin strapping to configure LED open-drain or EEPROM
48      presence. This is needed for devices with incorrect configuration or when
49      the OEM has decided not to use pin strapping and falls back to SW regs.
50
51  qca,led-open-drain:
52    $ref: /schemas/types.yaml#/definitions/flag
53    description:
54      Set LEDs to open-drain mode. This requires the qca,ignore-power-on-sel to
55      be set, otherwise the driver will fail at probe. This is required if the
56      OEM does not use pin strapping to set this mode and prefers to set it
57      using SW regs. The pin strappings related to LED open-drain mode are
58      B68 on the QCA832x and B49 on the QCA833x.
59
60  mdio:
61    $ref: /schemas/net/mdio.yaml#
62    unevaluatedProperties: false
63    description: Qca8k switch have an internal mdio to access switch port.
64                 If this is not present, the legacy mapping is used and the
65                 internal mdio access is used.
66                 With the legacy mapping the reg corresponding to the internal
67                 mdio is the switch reg with an offset of -1.
68
69patternProperties:
70  "^(ethernet-)?ports$":
71    type: object
72    properties:
73      '#address-cells':
74        const: 1
75      '#size-cells':
76        const: 0
77
78    patternProperties:
79      "^(ethernet-)?port@[0-6]$":
80        type: object
81        description: Ethernet switch ports
82
83        properties:
84          reg:
85            description: Port number
86
87          label:
88            description:
89              Describes the label associated with this port, which will become
90              the netdev name
91            $ref: /schemas/types.yaml#/definitions/string
92
93          link:
94            description:
95              Should be a list of phandles to other switch's DSA port. This
96              port is used as the outgoing port towards the phandle ports. The
97              full routing information must be given, not just the one hop
98              routes to neighbouring switches
99            $ref: /schemas/types.yaml#/definitions/phandle-array
100
101          ethernet:
102            description:
103              Should be a phandle to a valid Ethernet device node.  This host
104              device is what the switch port is connected to
105            $ref: /schemas/types.yaml#/definitions/phandle
106
107          phy-handle: true
108
109          phy-mode: true
110
111          fixed-link: true
112
113          mac-address: true
114
115          sfp: true
116
117          qca,sgmii-rxclk-falling-edge:
118            $ref: /schemas/types.yaml#/definitions/flag
119            description:
120              Set the receive clock phase to falling edge. Mostly commonly used on
121              the QCA8327 with CPU port 0 set to SGMII.
122
123          qca,sgmii-txclk-falling-edge:
124            $ref: /schemas/types.yaml#/definitions/flag
125            description:
126              Set the transmit clock phase to falling edge.
127
128          qca,sgmii-enable-pll:
129            $ref: /schemas/types.yaml#/definitions/flag
130            description:
131              For SGMII CPU port, explicitly enable PLL, TX and RX chain along with
132              Signal Detection. On the QCA8327 this should not be enabled, otherwise
133              the SGMII port will not initialize. When used on the QCA8337, revision 3
134              or greater, a warning will be displayed. When the CPU port is set to
135              SGMII on the QCA8337, it is advised to set this unless a communication
136              issue is observed.
137
138        required:
139          - reg
140
141        additionalProperties: false
142
143oneOf:
144  - required:
145      - ports
146  - required:
147      - ethernet-ports
148
149required:
150  - compatible
151  - reg
152
153additionalProperties: true
154
155examples:
156  - |
157    #include <dt-bindings/gpio/gpio.h>
158
159    mdio {
160        #address-cells = <1>;
161        #size-cells = <0>;
162
163        external_phy_port1: ethernet-phy@0 {
164            reg = <0>;
165        };
166
167        external_phy_port2: ethernet-phy@1 {
168            reg = <1>;
169        };
170
171        external_phy_port3: ethernet-phy@2 {
172            reg = <2>;
173        };
174
175        external_phy_port4: ethernet-phy@3 {
176            reg = <3>;
177        };
178
179        external_phy_port5: ethernet-phy@4 {
180            reg = <4>;
181        };
182
183        switch@10 {
184            compatible = "qca,qca8337";
185            #address-cells = <1>;
186            #size-cells = <0>;
187            reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
188            reg = <0x10>;
189
190            ports {
191                #address-cells = <1>;
192                #size-cells = <0>;
193
194                port@0 {
195                    reg = <0>;
196                    label = "cpu";
197                    ethernet = <&gmac1>;
198                    phy-mode = "rgmii";
199
200                    fixed-link {
201                        speed = <1000>;
202                        full-duplex;
203                    };
204                };
205
206                port@1 {
207                    reg = <1>;
208                    label = "lan1";
209                    phy-handle = <&external_phy_port1>;
210                };
211
212                port@2 {
213                    reg = <2>;
214                    label = "lan2";
215                    phy-handle = <&external_phy_port2>;
216                };
217
218                port@3 {
219                    reg = <3>;
220                    label = "lan3";
221                    phy-handle = <&external_phy_port3>;
222                };
223
224                port@4 {
225                    reg = <4>;
226                    label = "lan4";
227                    phy-handle = <&external_phy_port4>;
228                };
229
230                port@5 {
231                    reg = <5>;
232                    label = "wan";
233                    phy-handle = <&external_phy_port5>;
234                };
235            };
236        };
237    };
238  - |
239    #include <dt-bindings/gpio/gpio.h>
240
241    mdio {
242        #address-cells = <1>;
243        #size-cells = <0>;
244
245        switch@10 {
246            compatible = "qca,qca8337";
247            #address-cells = <1>;
248            #size-cells = <0>;
249            reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
250            reg = <0x10>;
251
252            ports {
253                #address-cells = <1>;
254                #size-cells = <0>;
255
256                port@0 {
257                    reg = <0>;
258                    label = "cpu";
259                    ethernet = <&gmac1>;
260                    phy-mode = "rgmii";
261
262                    fixed-link {
263                        speed = <1000>;
264                        full-duplex;
265                    };
266                };
267
268                port@1 {
269                    reg = <1>;
270                    label = "lan1";
271                    phy-mode = "internal";
272                    phy-handle = <&internal_phy_port1>;
273                };
274
275                port@2 {
276                    reg = <2>;
277                    label = "lan2";
278                    phy-mode = "internal";
279                    phy-handle = <&internal_phy_port2>;
280                };
281
282                port@3 {
283                    reg = <3>;
284                    label = "lan3";
285                    phy-mode = "internal";
286                    phy-handle = <&internal_phy_port3>;
287                };
288
289                port@4 {
290                    reg = <4>;
291                    label = "lan4";
292                    phy-mode = "internal";
293                    phy-handle = <&internal_phy_port4>;
294                };
295
296                port@5 {
297                    reg = <5>;
298                    label = "wan";
299                    phy-mode = "internal";
300                    phy-handle = <&internal_phy_port5>;
301                };
302
303                port@6 {
304                    reg = <0>;
305                    label = "cpu";
306                    ethernet = <&gmac1>;
307                    phy-mode = "sgmii";
308
309                    qca,sgmii-rxclk-falling-edge;
310
311                    fixed-link {
312                        speed = <1000>;
313                        full-duplex;
314                    };
315                };
316            };
317
318            mdio {
319                #address-cells = <1>;
320                #size-cells = <0>;
321
322                internal_phy_port1: ethernet-phy@0 {
323                    reg = <0>;
324                };
325
326                internal_phy_port2: ethernet-phy@1 {
327                    reg = <1>;
328                };
329
330                internal_phy_port3: ethernet-phy@2 {
331                    reg = <2>;
332                };
333
334                internal_phy_port4: ethernet-phy@3 {
335                    reg = <3>;
336                };
337
338                internal_phy_port5: ethernet-phy@4 {
339                    reg = <4>;
340                };
341            };
342        };
343    };
344