1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/dsa/qca8k.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Atheros QCA83xx switch family
8
9maintainers:
10  - John Crispin <john@phrozen.org>
11
12description:
13  If the QCA8K switch is connect to an SoC's external mdio-bus, each subnode
14  describing a port needs to have a valid phandle referencing the internal PHY
15  it is connected to. This is because there is no N:N mapping of port and PHY
16  ID. To declare the internal mdio-bus configuration, declare an MDIO node in
17  the switch node and declare the phandle for the port, referencing the internal
18  PHY it is connected to. In this config, an internal mdio-bus is registered and
19  the MDIO master is used for communication. Mixed external and internal
20  mdio-bus configurations are not supported by the hardware.
21
22properties:
23  compatible:
24    oneOf:
25      - enum:
26          - qca,qca8327
27          - qca,qca8328
28          - qca,qca8334
29          - qca,qca8337
30    description: |
31      qca,qca8328: referenced as AR8328(N)-AK1(A/B) QFN 176 pin package
32      qca,qca8327: referenced as AR8327(N)-AL1A DR-QFN 148 pin package
33      qca,qca8334: referenced as QCA8334-AL3C QFN 88 pin package
34      qca,qca8337: referenced as QCA8337N-AL3(B/C) DR-QFN 148 pin package
35
36  reg:
37    maxItems: 1
38
39  reset-gpios:
40    description:
41      GPIO to be used to reset the whole device
42    maxItems: 1
43
44  qca,ignore-power-on-sel:
45    $ref: /schemas/types.yaml#/definitions/flag
46    description:
47      Ignore power-on pin strapping to configure LED open-drain or EEPROM
48      presence. This is needed for devices with incorrect configuration or when
49      the OEM has decided not to use pin strapping and falls back to SW regs.
50
51  qca,led-open-drain:
52    $ref: /schemas/types.yaml#/definitions/flag
53    description:
54      Set LEDs to open-drain mode. This requires the qca,ignore-power-on-sel to
55      be set, otherwise the driver will fail at probe. This is required if the
56      OEM does not use pin strapping to set this mode and prefers to set it
57      using SW regs. The pin strappings related to LED open-drain mode are
58      B68 on the QCA832x and B49 on the QCA833x.
59
60  mdio:
61    type: object
62    description: Qca8k switch have an internal mdio to access switch port.
63                 If this is not present, the legacy mapping is used and the
64                 internal mdio access is used.
65                 With the legacy mapping the reg corresponding to the internal
66                 mdio is the switch reg with an offset of -1.
67
68    properties:
69      '#address-cells':
70        const: 1
71      '#size-cells':
72        const: 0
73
74    patternProperties:
75      "^(ethernet-)?phy@[0-4]$":
76        type: object
77
78        allOf:
79          - $ref: "http://devicetree.org/schemas/net/mdio.yaml#"
80
81        properties:
82          reg:
83            maxItems: 1
84
85        required:
86          - reg
87
88patternProperties:
89  "^(ethernet-)?ports$":
90    type: object
91    properties:
92      '#address-cells':
93        const: 1
94      '#size-cells':
95        const: 0
96
97    patternProperties:
98      "^(ethernet-)?port@[0-6]$":
99        type: object
100        description: Ethernet switch ports
101
102        properties:
103          reg:
104            description: Port number
105
106          label:
107            description:
108              Describes the label associated with this port, which will become
109              the netdev name
110            $ref: /schemas/types.yaml#/definitions/string
111
112          link:
113            description:
114              Should be a list of phandles to other switch's DSA port. This
115              port is used as the outgoing port towards the phandle ports. The
116              full routing information must be given, not just the one hop
117              routes to neighbouring switches
118            $ref: /schemas/types.yaml#/definitions/phandle-array
119
120          ethernet:
121            description:
122              Should be a phandle to a valid Ethernet device node.  This host
123              device is what the switch port is connected to
124            $ref: /schemas/types.yaml#/definitions/phandle
125
126          phy-handle: true
127
128          phy-mode: true
129
130          fixed-link: true
131
132          mac-address: true
133
134          sfp: true
135
136          qca,sgmii-rxclk-falling-edge:
137            $ref: /schemas/types.yaml#/definitions/flag
138            description:
139              Set the receive clock phase to falling edge. Mostly commonly used on
140              the QCA8327 with CPU port 0 set to SGMII.
141
142          qca,sgmii-txclk-falling-edge:
143            $ref: /schemas/types.yaml#/definitions/flag
144            description:
145              Set the transmit clock phase to falling edge.
146
147          qca,sgmii-enable-pll:
148            $ref: /schemas/types.yaml#/definitions/flag
149            description:
150              For SGMII CPU port, explicitly enable PLL, TX and RX chain along with
151              Signal Detection. On the QCA8327 this should not be enabled, otherwise
152              the SGMII port will not initialize. When used on the QCA8337, revision 3
153              or greater, a warning will be displayed. When the CPU port is set to
154              SGMII on the QCA8337, it is advised to set this unless a communication
155              issue is observed.
156
157        required:
158          - reg
159
160        additionalProperties: false
161
162oneOf:
163  - required:
164      - ports
165  - required:
166      - ethernet-ports
167
168required:
169  - compatible
170  - reg
171
172additionalProperties: true
173
174examples:
175  - |
176    #include <dt-bindings/gpio/gpio.h>
177
178    mdio {
179        #address-cells = <1>;
180        #size-cells = <0>;
181
182        external_phy_port1: ethernet-phy@0 {
183            reg = <0>;
184        };
185
186        external_phy_port2: ethernet-phy@1 {
187            reg = <1>;
188        };
189
190        external_phy_port3: ethernet-phy@2 {
191            reg = <2>;
192        };
193
194        external_phy_port4: ethernet-phy@3 {
195            reg = <3>;
196        };
197
198        external_phy_port5: ethernet-phy@4 {
199            reg = <4>;
200        };
201
202        switch@10 {
203            compatible = "qca,qca8337";
204            #address-cells = <1>;
205            #size-cells = <0>;
206            reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
207            reg = <0x10>;
208
209            ports {
210                #address-cells = <1>;
211                #size-cells = <0>;
212
213                port@0 {
214                    reg = <0>;
215                    label = "cpu";
216                    ethernet = <&gmac1>;
217                    phy-mode = "rgmii";
218
219                    fixed-link {
220                        speed = <1000>;
221                        full-duplex;
222                    };
223                };
224
225                port@1 {
226                    reg = <1>;
227                    label = "lan1";
228                    phy-handle = <&external_phy_port1>;
229                };
230
231                port@2 {
232                    reg = <2>;
233                    label = "lan2";
234                    phy-handle = <&external_phy_port2>;
235                };
236
237                port@3 {
238                    reg = <3>;
239                    label = "lan3";
240                    phy-handle = <&external_phy_port3>;
241                };
242
243                port@4 {
244                    reg = <4>;
245                    label = "lan4";
246                    phy-handle = <&external_phy_port4>;
247                };
248
249                port@5 {
250                    reg = <5>;
251                    label = "wan";
252                    phy-handle = <&external_phy_port5>;
253                };
254            };
255        };
256    };
257  - |
258    #include <dt-bindings/gpio/gpio.h>
259
260    mdio {
261        #address-cells = <1>;
262        #size-cells = <0>;
263
264        switch@10 {
265            compatible = "qca,qca8337";
266            #address-cells = <1>;
267            #size-cells = <0>;
268            reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
269            reg = <0x10>;
270
271            ports {
272                #address-cells = <1>;
273                #size-cells = <0>;
274
275                port@0 {
276                    reg = <0>;
277                    label = "cpu";
278                    ethernet = <&gmac1>;
279                    phy-mode = "rgmii";
280
281                    fixed-link {
282                        speed = <1000>;
283                        full-duplex;
284                    };
285                };
286
287                port@1 {
288                    reg = <1>;
289                    label = "lan1";
290                    phy-mode = "internal";
291                    phy-handle = <&internal_phy_port1>;
292                };
293
294                port@2 {
295                    reg = <2>;
296                    label = "lan2";
297                    phy-mode = "internal";
298                    phy-handle = <&internal_phy_port2>;
299                };
300
301                port@3 {
302                    reg = <3>;
303                    label = "lan3";
304                    phy-mode = "internal";
305                    phy-handle = <&internal_phy_port3>;
306                };
307
308                port@4 {
309                    reg = <4>;
310                    label = "lan4";
311                    phy-mode = "internal";
312                    phy-handle = <&internal_phy_port4>;
313                };
314
315                port@5 {
316                    reg = <5>;
317                    label = "wan";
318                    phy-mode = "internal";
319                    phy-handle = <&internal_phy_port5>;
320                };
321
322                port@6 {
323                    reg = <0>;
324                    label = "cpu";
325                    ethernet = <&gmac1>;
326                    phy-mode = "sgmii";
327
328                    qca,sgmii-rxclk-falling-edge;
329
330                    fixed-link {
331                        speed = <1000>;
332                        full-duplex;
333                    };
334                };
335            };
336
337            mdio {
338                #address-cells = <1>;
339                #size-cells = <0>;
340
341                internal_phy_port1: ethernet-phy@0 {
342                    reg = <0>;
343                };
344
345                internal_phy_port2: ethernet-phy@1 {
346                    reg = <1>;
347                };
348
349                internal_phy_port3: ethernet-phy@2 {
350                    reg = <2>;
351                };
352
353                internal_phy_port4: ethernet-phy@3 {
354                    reg = <3>;
355                };
356
357                internal_phy_port5: ethernet-phy@4 {
358                    reg = <4>;
359                };
360            };
361        };
362    };
363