1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/dsa/nxp,sja1105.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NXP SJA1105 Automotive Ethernet Switch Family Device Tree Bindings
8
9description:
10  The SJA1105 SPI interface requires a CS-to-CLK time (t2 in UM10944.pdf) of at
11  least one half of t_CLK. At an SPI frequency of 1MHz, this means a minimum
12  cs_sck_delay of 500ns. Ensuring that this SPI timing requirement is observed
13  depends on the SPI bus master driver.
14
15allOf:
16  - $ref: "dsa.yaml#"
17
18maintainers:
19  - Vladimir Oltean <vladimir.oltean@nxp.com>
20
21properties:
22  compatible:
23    enum:
24      - nxp,sja1105e
25      - nxp,sja1105t
26      - nxp,sja1105p
27      - nxp,sja1105q
28      - nxp,sja1105r
29      - nxp,sja1105s
30      - nxp,sja1110a
31      - nxp,sja1110b
32      - nxp,sja1110c
33      - nxp,sja1110d
34
35  reg:
36    maxItems: 1
37
38  # Optional container node for the 2 internal MDIO buses of the SJA1110
39  # (one for the internal 100base-T1 PHYs and the other for the single
40  # 100base-TX PHY). The "reg" property does not have physical significance.
41  # The PHY addresses to port correspondence is as follows: for 100base-T1,
42  # port 5 has PHY 1, port 6 has PHY 2 etc, while for 100base-TX, port 1 has
43  # PHY 1.
44  mdios:
45    type: object
46
47    properties:
48      '#address-cells':
49        const: 1
50      '#size-cells':
51        const: 0
52
53    patternProperties:
54      "^mdio@[0-1]$":
55        $ref: /schemas/net/mdio.yaml#
56        unevaluatedProperties: false
57
58        properties:
59          compatible:
60            oneOf:
61              - enum:
62                  - nxp,sja1110-base-t1-mdio
63                  - nxp,sja1110-base-tx-mdio
64
65          reg:
66            oneOf:
67              - enum:
68                  - 0
69                  - 1
70
71        required:
72          - compatible
73          - reg
74
75patternProperties:
76  "^(ethernet-)?ports$":
77    patternProperties:
78      "^(ethernet-)?port@[0-9]+$":
79        allOf:
80          - if:
81              properties:
82                phy-mode:
83                  contains:
84                    enum:
85                      - rgmii
86                      - rgmii-rxid
87                      - rgmii-txid
88                      - rgmii-id
89            then:
90              properties:
91                rx-internal-delay-ps:
92                  $ref: "#/$defs/internal-delay-ps"
93                tx-internal-delay-ps:
94                  $ref: "#/$defs/internal-delay-ps"
95
96required:
97  - compatible
98  - reg
99
100$defs:
101  internal-delay-ps:
102    description:
103      Disable tunable delay lines using 0 ps, or enable them and select
104      the phase between 1640 ps (73.8 degree shift at 1Gbps) and 2260 ps
105      (101.7 degree shift) in increments of 0.9 degrees (20 ps).
106    enum:
107      [0, 1640, 1660, 1680, 1700, 1720, 1740, 1760, 1780, 1800, 1820, 1840,
108       1860, 1880, 1900, 1920, 1940, 1960, 1980, 2000, 2020, 2040, 2060, 2080,
109       2100, 2120, 2140, 2160, 2180, 2200, 2220, 2240, 2260]
110
111unevaluatedProperties: false
112
113examples:
114  - |
115    spi {
116            #address-cells = <1>;
117            #size-cells = <0>;
118
119            ethernet-switch@1 {
120                    reg = <0x1>;
121                    compatible = "nxp,sja1105t";
122
123                    ethernet-ports {
124                            #address-cells = <1>;
125                            #size-cells = <0>;
126
127                            port@0 {
128                                    phy-handle = <&rgmii_phy6>;
129                                    phy-mode = "rgmii-id";
130                                    rx-internal-delay-ps = <0>;
131                                    tx-internal-delay-ps = <0>;
132                                    reg = <0>;
133                            };
134
135                            port@1 {
136                                    phy-handle = <&rgmii_phy3>;
137                                    phy-mode = "rgmii-id";
138                                    rx-internal-delay-ps = <0>;
139                                    tx-internal-delay-ps = <0>;
140                                    reg = <1>;
141                            };
142
143                            port@2 {
144                                    phy-handle = <&rgmii_phy4>;
145                                    phy-mode = "rgmii-id";
146                                    rx-internal-delay-ps = <0>;
147                                    tx-internal-delay-ps = <0>;
148                                    reg = <2>;
149                            };
150
151                            port@3 {
152                                    phy-handle = <&rgmii_phy4>;
153                                    phy-mode = "rgmii-id";
154                                    rx-internal-delay-ps = <0>;
155                                    tx-internal-delay-ps = <0>;
156                                    reg = <3>;
157                            };
158
159                            port@4 {
160                                    ethernet = <&enet2>;
161                                    phy-mode = "rgmii";
162                                    rx-internal-delay-ps = <0>;
163                                    tx-internal-delay-ps = <0>;
164                                    reg = <4>;
165
166                                    fixed-link {
167                                            speed = <1000>;
168                                            full-duplex;
169                                    };
170                            };
171                    };
172            };
173    };
174