1# SPDX-License-Identifier: GPL-2.0-only 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/net/dsa/microchip,ksz.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Microchip KSZ Series Ethernet switches 8 9maintainers: 10 - Marek Vasut <marex@denx.de> 11 - Woojung Huh <Woojung.Huh@microchip.com> 12 13allOf: 14 - $ref: dsa.yaml# 15 - $ref: /schemas/spi/spi-peripheral-props.yaml# 16 17properties: 18 # See Documentation/devicetree/bindings/net/dsa/dsa.yaml for a list of additional 19 # required and optional properties. 20 compatible: 21 enum: 22 - microchip,ksz8765 23 - microchip,ksz8794 24 - microchip,ksz8795 25 - microchip,ksz8863 26 - microchip,ksz8873 27 - microchip,ksz9477 28 - microchip,ksz9897 29 - microchip,ksz9896 30 - microchip,ksz9567 31 - microchip,ksz8565 32 - microchip,ksz9893 33 - microchip,ksz9563 34 - microchip,ksz8563 35 36 reset-gpios: 37 description: 38 Should be a gpio specifier for a reset line. 39 maxItems: 1 40 41 microchip,synclko-125: 42 $ref: /schemas/types.yaml#/definitions/flag 43 description: 44 Set if the output SYNCLKO frequency should be set to 125MHz instead of 25MHz. 45 46 microchip,synclko-disable: 47 $ref: /schemas/types.yaml#/definitions/flag 48 description: 49 Set if the output SYNCLKO clock should be disabled. Do not mix with 50 microchip,synclko-125. 51 52required: 53 - compatible 54 - reg 55 56unevaluatedProperties: false 57 58examples: 59 - | 60 #include <dt-bindings/gpio/gpio.h> 61 62 // Ethernet switch connected via SPI to the host, CPU port wired to eth0: 63 eth0 { 64 fixed-link { 65 speed = <1000>; 66 full-duplex; 67 }; 68 }; 69 70 spi0 { 71 #address-cells = <1>; 72 #size-cells = <0>; 73 74 pinctrl-0 = <&pinctrl_spi_ksz>; 75 cs-gpios = <&pioC 25 0>; 76 id = <1>; 77 78 ksz9477: switch@0 { 79 compatible = "microchip,ksz9477"; 80 reg = <0>; 81 reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; 82 83 spi-max-frequency = <44000000>; 84 85 ethernet-ports { 86 #address-cells = <1>; 87 #size-cells = <0>; 88 port@0 { 89 reg = <0>; 90 label = "lan1"; 91 }; 92 port@1 { 93 reg = <1>; 94 label = "lan2"; 95 }; 96 port@2 { 97 reg = <2>; 98 label = "lan3"; 99 }; 100 port@3 { 101 reg = <3>; 102 label = "lan4"; 103 }; 104 port@4 { 105 reg = <4>; 106 label = "lan5"; 107 }; 108 port@5 { 109 reg = <5>; 110 label = "cpu"; 111 ethernet = <ð0>; 112 fixed-link { 113 speed = <1000>; 114 full-duplex; 115 }; 116 }; 117 }; 118 }; 119 120 ksz8565: switch@1 { 121 compatible = "microchip,ksz8565"; 122 reg = <1>; 123 124 spi-max-frequency = <44000000>; 125 126 ethernet-ports { 127 #address-cells = <1>; 128 #size-cells = <0>; 129 port@0 { 130 reg = <0>; 131 label = "lan1"; 132 }; 133 port@1 { 134 reg = <1>; 135 label = "lan2"; 136 }; 137 port@2 { 138 reg = <2>; 139 label = "lan3"; 140 }; 141 port@3 { 142 reg = <3>; 143 label = "lan4"; 144 }; 145 port@6 { 146 reg = <6>; 147 label = "cpu"; 148 ethernet = <ð0>; 149 fixed-link { 150 speed = <1000>; 151 full-duplex; 152 }; 153 }; 154 }; 155 }; 156 }; 157... 158