1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/net/dsa/mediatek,mt7530.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Mediatek MT7530 and MT7531 Ethernet Switches 8 9maintainers: 10 - Arınç ÜNAL <arinc.unal@arinc9.com> 11 - Landen Chao <Landen.Chao@mediatek.com> 12 - DENG Qingfang <dqfext@gmail.com> 13 - Sean Wang <sean.wang@mediatek.com> 14 15description: | 16 There are two versions of MT7530, standalone and in a multi-chip module. 17 18 MT7530 is a part of the multi-chip module in MT7620AN, MT7620DA, MT7620DAN, 19 MT7620NN, MT7621AT, MT7621DAT, MT7621ST and MT7623AI SoCs. 20 21 MT7530 in MT7620AN, MT7620DA, MT7620DAN and MT7620NN SoCs has got 10/100 PHYs 22 and the switch registers are directly mapped into SoC's memory map rather than 23 using MDIO. The DSA driver currently doesn't support this. 24 25 There is only the standalone version of MT7531. 26 27 Port 5 on MT7530 has got various ways of configuration. 28 29 For standalone MT7530: 30 31 - Port 5 can be used as a CPU port. 32 33 - PHY 0 or 4 of the switch can be muxed to connect to the gmac of the SoC 34 which port 5 is wired to. Usually used for connecting the wan port 35 directly to the CPU to achieve 2 Gbps routing in total. 36 37 The driver looks up the reg on the ethernet-phy node which the phy-handle 38 property refers to on the gmac node to mux the specified phy. 39 40 The driver requires the gmac of the SoC to have "mediatek,eth-mac" as the 41 compatible string and the reg must be 1. So, for now, only gmac1 of an 42 MediaTek SoC can benefit this. Banana Pi BPI-R2 suits this. 43 Check out example 5 for a similar configuration. 44 45 - Port 5 can be wired to an external phy. Port 5 becomes a DSA slave. 46 Check out example 7 for a similar configuration. 47 48 For multi-chip module MT7530: 49 50 - Port 5 can be used as a CPU port. 51 52 - PHY 0 or 4 of the switch can be muxed to connect to gmac1 of the SoC. 53 Usually used for connecting the wan port directly to the CPU to achieve 2 54 Gbps routing in total. 55 56 The driver looks up the reg on the ethernet-phy node which the phy-handle 57 property refers to on the gmac node to mux the specified phy. 58 59 For the MT7621 SoCs, rgmii2 group must be claimed with rgmii2 function. 60 Check out example 5. 61 62 - In case of an external phy wired to gmac1 of the SoC, port 5 must not be 63 enabled. 64 65 In case of muxing PHY 0 or 4, the external phy must not be enabled. 66 67 For the MT7621 SoCs, rgmii2 group must be claimed with rgmii2 function. 68 Check out example 6. 69 70 - Port 5 can be muxed to an external phy. Port 5 becomes a DSA slave. 71 The external phy must be wired TX to TX to gmac1 of the SoC for this to 72 work. Ubiquiti EdgeRouter X SFP is wired this way. 73 74 Muxing PHY 0 or 4 won't work when the external phy is connected TX to TX. 75 76 For the MT7621 SoCs, rgmii2 group must be claimed with gpio function. 77 Check out example 7. 78 79properties: 80 compatible: 81 oneOf: 82 - description: 83 Standalone MT7530 and multi-chip module MT7530 in MT7623AI SoC 84 const: mediatek,mt7530 85 86 - description: 87 Standalone MT7531 88 const: mediatek,mt7531 89 90 - description: 91 Multi-chip module MT7530 in MT7621AT, MT7621DAT and MT7621ST SoCs 92 const: mediatek,mt7621 93 94 reg: 95 maxItems: 1 96 97 core-supply: 98 description: 99 Phandle to the regulator node necessary for the core power. 100 101 "#gpio-cells": 102 const: 2 103 104 gpio-controller: 105 type: boolean 106 description: 107 If defined, LED controller of the MT7530 switch will run on GPIO mode. 108 109 There are 15 controllable pins. 110 port 0 LED 0..2 as GPIO 0..2 111 port 1 LED 0..2 as GPIO 3..5 112 port 2 LED 0..2 as GPIO 6..8 113 port 3 LED 0..2 as GPIO 9..11 114 port 4 LED 0..2 as GPIO 12..14 115 116 "#interrupt-cells": 117 const: 1 118 119 interrupt-controller: true 120 121 interrupts: 122 maxItems: 1 123 124 io-supply: 125 description: 126 Phandle to the regulator node necessary for the I/O power. 127 See Documentation/devicetree/bindings/regulator/mt6323-regulator.txt for 128 details for the regulator setup on these boards. 129 130 mediatek,mcm: 131 type: boolean 132 description: 133 Used for MT7621AT, MT7621DAT, MT7621ST and MT7623AI SoCs which the MT7530 134 switch is a part of the multi-chip module. 135 136 reset-gpios: 137 description: 138 GPIO to reset the switch. Use this if mediatek,mcm is not used. 139 This property is optional because some boards share the reset line with 140 other components which makes it impossible to probe the switch if the 141 reset line is used. 142 maxItems: 1 143 144 reset-names: 145 const: mcm 146 147 resets: 148 description: 149 Phandle pointing to the system reset controller with line index for the 150 ethsys. 151 maxItems: 1 152 153patternProperties: 154 "^(ethernet-)?ports$": 155 type: object 156 157 patternProperties: 158 "^(ethernet-)?port@[0-9]+$": 159 type: object 160 161 properties: 162 reg: 163 description: 164 Port address described must be 5 or 6 for CPU port and from 0 to 5 165 for user ports. 166 167 allOf: 168 - if: 169 required: [ ethernet ] 170 then: 171 properties: 172 reg: 173 enum: 174 - 5 175 - 6 176 177required: 178 - compatible 179 - reg 180 181$defs: 182 mt7530-dsa-port: 183 patternProperties: 184 "^(ethernet-)?ports$": 185 patternProperties: 186 "^(ethernet-)?port@[0-9]+$": 187 if: 188 required: [ ethernet ] 189 then: 190 if: 191 properties: 192 reg: 193 const: 5 194 then: 195 properties: 196 phy-mode: 197 enum: 198 - gmii 199 - mii 200 - rgmii 201 else: 202 properties: 203 phy-mode: 204 enum: 205 - rgmii 206 - trgmii 207 208 mt7531-dsa-port: 209 patternProperties: 210 "^(ethernet-)?ports$": 211 patternProperties: 212 "^(ethernet-)?port@[0-9]+$": 213 if: 214 required: [ ethernet ] 215 then: 216 if: 217 properties: 218 reg: 219 const: 5 220 then: 221 properties: 222 phy-mode: 223 enum: 224 - 1000base-x 225 - 2500base-x 226 - rgmii 227 - sgmii 228 else: 229 properties: 230 phy-mode: 231 enum: 232 - 1000base-x 233 - 2500base-x 234 - sgmii 235 236allOf: 237 - $ref: dsa.yaml#/$defs/ethernet-ports 238 - if: 239 required: 240 - mediatek,mcm 241 then: 242 properties: 243 reset-gpios: false 244 245 required: 246 - resets 247 - reset-names 248 249 - dependencies: 250 interrupt-controller: [ interrupts ] 251 252 - if: 253 properties: 254 compatible: 255 const: mediatek,mt7530 256 then: 257 $ref: "#/$defs/mt7530-dsa-port" 258 required: 259 - core-supply 260 - io-supply 261 262 - if: 263 properties: 264 compatible: 265 const: mediatek,mt7531 266 then: 267 $ref: "#/$defs/mt7531-dsa-port" 268 properties: 269 gpio-controller: false 270 mediatek,mcm: false 271 272 - if: 273 properties: 274 compatible: 275 const: mediatek,mt7621 276 then: 277 $ref: "#/$defs/mt7530-dsa-port" 278 required: 279 - mediatek,mcm 280 281unevaluatedProperties: false 282 283examples: 284 # Example 1: Standalone MT7530 285 - | 286 #include <dt-bindings/gpio/gpio.h> 287 288 mdio { 289 #address-cells = <1>; 290 #size-cells = <0>; 291 292 switch@1f { 293 compatible = "mediatek,mt7530"; 294 reg = <0x1f>; 295 296 reset-gpios = <&pio 33 0>; 297 298 core-supply = <&mt6323_vpa_reg>; 299 io-supply = <&mt6323_vemc3v3_reg>; 300 301 ethernet-ports { 302 #address-cells = <1>; 303 #size-cells = <0>; 304 305 port@0 { 306 reg = <0>; 307 label = "lan1"; 308 }; 309 310 port@1 { 311 reg = <1>; 312 label = "lan2"; 313 }; 314 315 port@2 { 316 reg = <2>; 317 label = "lan3"; 318 }; 319 320 port@3 { 321 reg = <3>; 322 label = "lan4"; 323 }; 324 325 port@4 { 326 reg = <4>; 327 label = "wan"; 328 }; 329 330 port@6 { 331 reg = <6>; 332 ethernet = <&gmac0>; 333 phy-mode = "rgmii"; 334 335 fixed-link { 336 speed = <1000>; 337 full-duplex; 338 pause; 339 }; 340 }; 341 }; 342 }; 343 }; 344 345 # Example 2: MT7530 in MT7623AI SoC 346 - | 347 #include <dt-bindings/reset/mt2701-resets.h> 348 349 mdio { 350 #address-cells = <1>; 351 #size-cells = <0>; 352 353 switch@1f { 354 compatible = "mediatek,mt7530"; 355 reg = <0x1f>; 356 357 mediatek,mcm; 358 resets = <ðsys MT2701_ETHSYS_MCM_RST>; 359 reset-names = "mcm"; 360 361 core-supply = <&mt6323_vpa_reg>; 362 io-supply = <&mt6323_vemc3v3_reg>; 363 364 ethernet-ports { 365 #address-cells = <1>; 366 #size-cells = <0>; 367 368 port@0 { 369 reg = <0>; 370 label = "lan1"; 371 }; 372 373 port@1 { 374 reg = <1>; 375 label = "lan2"; 376 }; 377 378 port@2 { 379 reg = <2>; 380 label = "lan3"; 381 }; 382 383 port@3 { 384 reg = <3>; 385 label = "lan4"; 386 }; 387 388 port@4 { 389 reg = <4>; 390 label = "wan"; 391 }; 392 393 port@6 { 394 reg = <6>; 395 ethernet = <&gmac0>; 396 phy-mode = "trgmii"; 397 398 fixed-link { 399 speed = <1000>; 400 full-duplex; 401 pause; 402 }; 403 }; 404 }; 405 }; 406 }; 407 408 # Example 3: Standalone MT7531 409 - | 410 #include <dt-bindings/gpio/gpio.h> 411 #include <dt-bindings/interrupt-controller/irq.h> 412 413 mdio { 414 #address-cells = <1>; 415 #size-cells = <0>; 416 417 switch@0 { 418 compatible = "mediatek,mt7531"; 419 reg = <0>; 420 421 reset-gpios = <&pio 54 0>; 422 423 interrupt-controller; 424 #interrupt-cells = <1>; 425 interrupt-parent = <&pio>; 426 interrupts = <53 IRQ_TYPE_LEVEL_HIGH>; 427 428 ethernet-ports { 429 #address-cells = <1>; 430 #size-cells = <0>; 431 432 port@0 { 433 reg = <0>; 434 label = "lan1"; 435 }; 436 437 port@1 { 438 reg = <1>; 439 label = "lan2"; 440 }; 441 442 port@2 { 443 reg = <2>; 444 label = "lan3"; 445 }; 446 447 port@3 { 448 reg = <3>; 449 label = "lan4"; 450 }; 451 452 port@4 { 453 reg = <4>; 454 label = "wan"; 455 }; 456 457 port@6 { 458 reg = <6>; 459 ethernet = <&gmac0>; 460 phy-mode = "2500base-x"; 461 462 fixed-link { 463 speed = <2500>; 464 full-duplex; 465 pause; 466 }; 467 }; 468 }; 469 }; 470 }; 471 472 # Example 4: MT7530 in MT7621AT, MT7621DAT and MT7621ST SoCs 473 - | 474 #include <dt-bindings/interrupt-controller/mips-gic.h> 475 #include <dt-bindings/reset/mt7621-reset.h> 476 477 mdio { 478 #address-cells = <1>; 479 #size-cells = <0>; 480 481 switch@1f { 482 compatible = "mediatek,mt7621"; 483 reg = <0x1f>; 484 485 mediatek,mcm; 486 resets = <&sysc MT7621_RST_MCM>; 487 reset-names = "mcm"; 488 489 interrupt-controller; 490 #interrupt-cells = <1>; 491 interrupt-parent = <&gic>; 492 interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>; 493 494 ethernet-ports { 495 #address-cells = <1>; 496 #size-cells = <0>; 497 498 port@0 { 499 reg = <0>; 500 label = "lan1"; 501 }; 502 503 port@1 { 504 reg = <1>; 505 label = "lan2"; 506 }; 507 508 port@2 { 509 reg = <2>; 510 label = "lan3"; 511 }; 512 513 port@3 { 514 reg = <3>; 515 label = "lan4"; 516 }; 517 518 port@4 { 519 reg = <4>; 520 label = "wan"; 521 }; 522 523 port@6 { 524 reg = <6>; 525 ethernet = <&gmac0>; 526 phy-mode = "trgmii"; 527 528 fixed-link { 529 speed = <1000>; 530 full-duplex; 531 pause; 532 }; 533 }; 534 }; 535 }; 536 }; 537 538 # Example 5: MT7621: mux MT7530's phy4 to SoC's gmac1 539 - | 540 #include <dt-bindings/interrupt-controller/mips-gic.h> 541 #include <dt-bindings/reset/mt7621-reset.h> 542 543 ethernet { 544 #address-cells = <1>; 545 #size-cells = <0>; 546 547 pinctrl-names = "default"; 548 pinctrl-0 = <&rgmii2_pins>; 549 550 mac@1 { 551 compatible = "mediatek,eth-mac"; 552 reg = <1>; 553 554 phy-mode = "rgmii"; 555 phy-handle = <&example5_ethphy4>; 556 }; 557 558 mdio { 559 #address-cells = <1>; 560 #size-cells = <0>; 561 562 /* MT7530's phy4 */ 563 example5_ethphy4: ethernet-phy@4 { 564 reg = <4>; 565 }; 566 567 switch@1f { 568 compatible = "mediatek,mt7621"; 569 reg = <0x1f>; 570 571 mediatek,mcm; 572 resets = <&sysc MT7621_RST_MCM>; 573 reset-names = "mcm"; 574 575 interrupt-controller; 576 #interrupt-cells = <1>; 577 interrupt-parent = <&gic>; 578 interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>; 579 580 ethernet-ports { 581 #address-cells = <1>; 582 #size-cells = <0>; 583 584 port@0 { 585 reg = <0>; 586 label = "lan1"; 587 }; 588 589 port@1 { 590 reg = <1>; 591 label = "lan2"; 592 }; 593 594 port@2 { 595 reg = <2>; 596 label = "lan3"; 597 }; 598 599 port@3 { 600 reg = <3>; 601 label = "lan4"; 602 }; 603 604 /* Commented out, phy4 is muxed to gmac1. 605 port@4 { 606 reg = <4>; 607 label = "wan"; 608 }; 609 */ 610 611 port@6 { 612 reg = <6>; 613 ethernet = <&gmac0>; 614 phy-mode = "trgmii"; 615 616 fixed-link { 617 speed = <1000>; 618 full-duplex; 619 pause; 620 }; 621 }; 622 }; 623 }; 624 }; 625 }; 626 627 # Example 6: MT7621: mux external phy to SoC's gmac1 628 - | 629 #include <dt-bindings/interrupt-controller/mips-gic.h> 630 #include <dt-bindings/reset/mt7621-reset.h> 631 632 ethernet { 633 #address-cells = <1>; 634 #size-cells = <0>; 635 636 pinctrl-names = "default"; 637 pinctrl-0 = <&rgmii2_pins>; 638 639 mac@1 { 640 compatible = "mediatek,eth-mac"; 641 reg = <1>; 642 643 phy-mode = "rgmii"; 644 phy-handle = <&example6_ethphy7>; 645 }; 646 647 mdio { 648 #address-cells = <1>; 649 #size-cells = <0>; 650 651 /* External PHY */ 652 example6_ethphy7: ethernet-phy@7 { 653 reg = <7>; 654 phy-mode = "rgmii"; 655 }; 656 657 switch@1f { 658 compatible = "mediatek,mt7621"; 659 reg = <0x1f>; 660 661 mediatek,mcm; 662 resets = <&sysc MT7621_RST_MCM>; 663 reset-names = "mcm"; 664 665 interrupt-controller; 666 #interrupt-cells = <1>; 667 interrupt-parent = <&gic>; 668 interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>; 669 670 ethernet-ports { 671 #address-cells = <1>; 672 #size-cells = <0>; 673 674 port@0 { 675 reg = <0>; 676 label = "lan1"; 677 }; 678 679 port@1 { 680 reg = <1>; 681 label = "lan2"; 682 }; 683 684 port@2 { 685 reg = <2>; 686 label = "lan3"; 687 }; 688 689 port@3 { 690 reg = <3>; 691 label = "lan4"; 692 }; 693 694 port@4 { 695 reg = <4>; 696 label = "wan"; 697 }; 698 699 port@6 { 700 reg = <6>; 701 ethernet = <&gmac0>; 702 phy-mode = "trgmii"; 703 704 fixed-link { 705 speed = <1000>; 706 full-duplex; 707 pause; 708 }; 709 }; 710 }; 711 }; 712 }; 713 }; 714 715 # Example 7: MT7621: mux external phy to MT7530's port 5 716 - | 717 #include <dt-bindings/interrupt-controller/mips-gic.h> 718 #include <dt-bindings/reset/mt7621-reset.h> 719 720 ethernet { 721 #address-cells = <1>; 722 #size-cells = <0>; 723 724 pinctrl-names = "default"; 725 pinctrl-0 = <&rgmii2_pins>; 726 727 mdio { 728 #address-cells = <1>; 729 #size-cells = <0>; 730 731 /* External PHY */ 732 example7_ethphy7: ethernet-phy@7 { 733 reg = <7>; 734 phy-mode = "rgmii"; 735 }; 736 737 switch@1f { 738 compatible = "mediatek,mt7621"; 739 reg = <0x1f>; 740 741 mediatek,mcm; 742 resets = <&sysc MT7621_RST_MCM>; 743 reset-names = "mcm"; 744 745 interrupt-controller; 746 #interrupt-cells = <1>; 747 interrupt-parent = <&gic>; 748 interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>; 749 750 ethernet-ports { 751 #address-cells = <1>; 752 #size-cells = <0>; 753 754 port@0 { 755 reg = <0>; 756 label = "lan1"; 757 }; 758 759 port@1 { 760 reg = <1>; 761 label = "lan2"; 762 }; 763 764 port@2 { 765 reg = <2>; 766 label = "lan3"; 767 }; 768 769 port@3 { 770 reg = <3>; 771 label = "lan4"; 772 }; 773 774 port@4 { 775 reg = <4>; 776 label = "wan"; 777 }; 778 779 port@5 { 780 reg = <5>; 781 label = "extphy"; 782 phy-mode = "rgmii-txid"; 783 phy-handle = <&example7_ethphy7>; 784 }; 785 786 port@6 { 787 reg = <6>; 788 ethernet = <&gmac0>; 789 phy-mode = "trgmii"; 790 791 fixed-link { 792 speed = <1000>; 793 full-duplex; 794 pause; 795 }; 796 }; 797 }; 798 }; 799 }; 800 }; 801