1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/dsa/mediatek,mt7530.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Mediatek MT7530 Ethernet switch
8
9maintainers:
10  - Sean Wang <sean.wang@mediatek.com>
11  - Landen Chao <Landen.Chao@mediatek.com>
12  - DENG Qingfang <dqfext@gmail.com>
13
14description: |
15  Port 5 of mt7530 and mt7621 switch is muxed between:
16  1. GMAC5: GMAC5 can interface with another external MAC or PHY.
17  2. PHY of port 0 or port 4: PHY interfaces with an external MAC like 2nd GMAC
18     of the SOC. Used in many setups where port 0/4 becomes the WAN port.
19     Note: On a MT7621 SOC with integrated switch: 2nd GMAC can only connected to
20       GMAC5 when the gpios for RGMII2 (GPIO 22-33) are not used and not
21       connected to external component!
22
23  Port 5 modes/configurations:
24  1. Port 5 is disabled and isolated: An external phy can interface to the 2nd
25     GMAC of the SOC.
26     In the case of a build-in MT7530 switch, port 5 shares the RGMII bus with 2nd
27     GMAC and an optional external phy. Mind the GPIO/pinctl settings of the SOC!
28  2. Port 5 is muxed to PHY of port 0/4: Port 0/4 interfaces with 2nd GMAC.
29     It is a simple MAC to PHY interface, port 5 needs to be setup for xMII mode
30     and RGMII delay.
31  3. Port 5 is muxed to GMAC5 and can interface to an external phy.
32     Port 5 becomes an extra switch port.
33     Only works on platform where external phy TX<->RX lines are swapped.
34     Like in the Ubiquiti ER-X-SFP.
35  4. Port 5 is muxed to GMAC5 and interfaces with the 2nd GAMC as 2nd CPU port.
36     Currently a 2nd CPU port is not supported by DSA code.
37
38  Depending on how the external PHY is wired:
39  1. normal: The PHY can only connect to 2nd GMAC but not to the switch
40  2. swapped: RGMII TX, RX are swapped; external phy interface with the switch as
41     a ethernet port. But can't interface to the 2nd GMAC.
42
43    Based on the DT the port 5 mode is configured.
44
45  Driver tries to lookup the phy-handle of the 2nd GMAC of the master device.
46  When phy-handle matches PHY of port 0 or 4 then port 5 set-up as mode 2.
47  phy-mode must be set, see also example 2 below!
48  * mt7621: phy-mode = "rgmii-txid";
49  * mt7623: phy-mode = "rgmii";
50
51  CPU-Ports need a phy-mode property:
52    Allowed values on mt7530 and mt7621:
53      - "rgmii"
54      - "trgmii"
55    On mt7531:
56      - "1000base-x"
57      - "2500base-x"
58      - "rgmii"
59      - "sgmii"
60
61
62properties:
63  compatible:
64    enum:
65      - mediatek,mt7530
66      - mediatek,mt7531
67      - mediatek,mt7621
68
69  core-supply:
70    description:
71      Phandle to the regulator node necessary for the core power.
72
73  "#gpio-cells":
74    const: 2
75
76  gpio-controller:
77    type: boolean
78    description:
79      if defined, MT7530's LED controller will run on GPIO mode.
80
81  "#interrupt-cells":
82    const: 1
83
84  interrupt-controller: true
85
86  interrupts:
87    maxItems: 1
88
89  io-supply:
90    description:
91      Phandle to the regulator node necessary for the I/O power.
92      See Documentation/devicetree/bindings/regulator/mt6323-regulator.txt
93      for details for the regulator setup on these boards.
94
95  mediatek,mcm:
96    type: boolean
97    description:
98      if defined, indicates that either MT7530 is the part on multi-chip
99      module belong to MT7623A has or the remotely standalone chip as the
100      function MT7623N reference board provided for.
101
102  reset-gpios:
103    maxItems: 1
104
105  reset-names:
106    const: mcm
107
108  resets:
109    description:
110      Phandle pointing to the system reset controller with line index for
111      the ethsys.
112    maxItems: 1
113
114patternProperties:
115  "^(ethernet-)?ports$":
116    type: object
117
118    patternProperties:
119      "^(ethernet-)?port@[0-9]+$":
120        type: object
121        description: Ethernet switch ports
122
123        unevaluatedProperties: false
124
125        properties:
126          reg:
127            description:
128              Port address described must be 5 or 6 for CPU port and from 0
129              to 5 for user ports.
130
131        allOf:
132          - $ref: dsa-port.yaml#
133          - if:
134              properties:
135                label:
136                  items:
137                    - const: cpu
138            then:
139              required:
140                - reg
141                - phy-mode
142
143required:
144  - compatible
145  - reg
146
147allOf:
148  - $ref: "dsa.yaml#"
149  - if:
150      required:
151        - mediatek,mcm
152    then:
153      required:
154        - resets
155        - reset-names
156
157  - dependencies:
158      interrupt-controller: [ interrupts ]
159
160  - if:
161      properties:
162        compatible:
163          items:
164            - const: mediatek,mt7530
165    then:
166      required:
167        - core-supply
168        - io-supply
169
170unevaluatedProperties: false
171
172examples:
173  - |
174    #include <dt-bindings/gpio/gpio.h>
175    mdio {
176        #address-cells = <1>;
177        #size-cells = <0>;
178        switch@0 {
179            compatible = "mediatek,mt7530";
180            reg = <0>;
181
182            core-supply = <&mt6323_vpa_reg>;
183            io-supply = <&mt6323_vemc3v3_reg>;
184            reset-gpios = <&pio 33 GPIO_ACTIVE_HIGH>;
185
186            ethernet-ports {
187                #address-cells = <1>;
188                #size-cells = <0>;
189                port@0 {
190                    reg = <0>;
191                    label = "lan0";
192                };
193
194                port@1 {
195                    reg = <1>;
196                    label = "lan1";
197                };
198
199                port@2 {
200                    reg = <2>;
201                    label = "lan2";
202                };
203
204                port@3 {
205                    reg = <3>;
206                    label = "lan3";
207                };
208
209                port@4 {
210                    reg = <4>;
211                    label = "wan";
212                };
213
214                port@6 {
215                    reg = <6>;
216                    label = "cpu";
217                    ethernet = <&gmac0>;
218                    phy-mode = "trgmii";
219                    fixed-link {
220                        speed = <1000>;
221                        full-duplex;
222                    };
223                };
224            };
225        };
226    };
227
228  - |
229    //Example 2: MT7621: Port 4 is WAN port: 2nd GMAC -> Port 5 -> PHY port 4.
230
231    ethernet {
232        #address-cells = <1>;
233        #size-cells = <0>;
234        gmac0: mac@0 {
235            compatible = "mediatek,eth-mac";
236            reg = <0>;
237            phy-mode = "rgmii";
238
239            fixed-link {
240                speed = <1000>;
241                full-duplex;
242                pause;
243            };
244        };
245
246        gmac1: mac@1 {
247            compatible = "mediatek,eth-mac";
248            reg = <1>;
249            phy-mode = "rgmii-txid";
250            phy-handle = <&phy4>;
251        };
252
253        mdio: mdio-bus {
254            #address-cells = <1>;
255            #size-cells = <0>;
256
257            /* Internal phy */
258            phy4: ethernet-phy@4 {
259                reg = <4>;
260            };
261
262            mt7530: switch@1f {
263                compatible = "mediatek,mt7621";
264                reg = <0x1f>;
265                mediatek,mcm;
266
267                resets = <&rstctrl 2>;
268                reset-names = "mcm";
269
270                ethernet-ports {
271                    #address-cells = <1>;
272                    #size-cells = <0>;
273
274                    port@0 {
275                        reg = <0>;
276                        label = "lan0";
277                    };
278
279                    port@1 {
280                        reg = <1>;
281                        label = "lan1";
282                    };
283
284                    port@2 {
285                        reg = <2>;
286                        label = "lan2";
287                    };
288
289                    port@3 {
290                        reg = <3>;
291                        label = "lan3";
292                    };
293
294                    /* Commented out. Port 4 is handled by 2nd GMAC.
295                    port@4 {
296                        reg = <4>;
297                        label = "lan4";
298                    };
299                    */
300
301                    port@6 {
302                        reg = <6>;
303                        label = "cpu";
304                        ethernet = <&gmac0>;
305                        phy-mode = "rgmii";
306
307                        fixed-link {
308                            speed = <1000>;
309                            full-duplex;
310                            pause;
311                        };
312                    };
313                };
314            };
315        };
316    };
317
318  - |
319    //Example 3: MT7621: Port 5 is connected to external PHY: Port 5 -> external PHY.
320
321    ethernet {
322        #address-cells = <1>;
323        #size-cells = <0>;
324        gmac_0: mac@0 {
325            compatible = "mediatek,eth-mac";
326            reg = <0>;
327            phy-mode = "rgmii";
328
329            fixed-link {
330                speed = <1000>;
331                full-duplex;
332                pause;
333            };
334        };
335
336        mdio0: mdio-bus {
337            #address-cells = <1>;
338            #size-cells = <0>;
339
340            /* External phy */
341            ephy5: ethernet-phy@7 {
342                reg = <7>;
343            };
344
345            switch@1f {
346                compatible = "mediatek,mt7621";
347                reg = <0x1f>;
348                mediatek,mcm;
349
350                resets = <&rstctrl 2>;
351                reset-names = "mcm";
352
353                ethernet-ports {
354                    #address-cells = <1>;
355                    #size-cells = <0>;
356
357                    port@0 {
358                        reg = <0>;
359                        label = "lan0";
360                    };
361
362                    port@1 {
363                        reg = <1>;
364                        label = "lan1";
365                    };
366
367                    port@2 {
368                        reg = <2>;
369                        label = "lan2";
370                    };
371
372                    port@3 {
373                        reg = <3>;
374                        label = "lan3";
375                    };
376
377                    port@4 {
378                        reg = <4>;
379                        label = "lan4";
380                    };
381
382                    port@5 {
383                        reg = <5>;
384                        label = "lan5";
385                        phy-mode = "rgmii";
386                        phy-handle = <&ephy5>;
387                    };
388
389                    cpu_port0: port@6 {
390                        reg = <6>;
391                        label = "cpu";
392                        ethernet = <&gmac_0>;
393                        phy-mode = "rgmii";
394
395                        fixed-link {
396                            speed = <1000>;
397                            full-duplex;
398                            pause;
399                        };
400                    };
401                };
402            };
403        };
404    };
405