1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/net/dsa/mediatek,mt7530.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Mediatek MT7530 and MT7531 Ethernet Switches 8 9maintainers: 10 - Arınç ÜNAL <arinc.unal@arinc9.com> 11 - Landen Chao <Landen.Chao@mediatek.com> 12 - DENG Qingfang <dqfext@gmail.com> 13 - Sean Wang <sean.wang@mediatek.com> 14 15description: | 16 There are two versions of MT7530, standalone and in a multi-chip module. 17 18 MT7530 is a part of the multi-chip module in MT7620AN, MT7620DA, MT7620DAN, 19 MT7620NN, MT7621AT, MT7621DAT, MT7621ST and MT7623AI SoCs. 20 21 MT7530 in MT7620AN, MT7620DA, MT7620DAN and MT7620NN SoCs has got 10/100 PHYs 22 and the switch registers are directly mapped into SoC's memory map rather than 23 using MDIO. The DSA driver currently doesn't support this. 24 25 There is only the standalone version of MT7531. 26 27 Port 5 on MT7530 has got various ways of configuration. 28 29 For standalone MT7530: 30 31 - Port 5 can be used as a CPU port. 32 33 - PHY 0 or 4 of the switch can be muxed to connect to the gmac of the SoC 34 which port 5 is wired to. Usually used for connecting the wan port 35 directly to the CPU to achieve 2 Gbps routing in total. 36 37 The driver looks up the reg on the ethernet-phy node which the phy-handle 38 property refers to on the gmac node to mux the specified phy. 39 40 The driver requires the gmac of the SoC to have "mediatek,eth-mac" as the 41 compatible string and the reg must be 1. So, for now, only gmac1 of an 42 MediaTek SoC can benefit this. Banana Pi BPI-R2 suits this. 43 Check out example 5 for a similar configuration. 44 45 - Port 5 can be wired to an external phy. Port 5 becomes a DSA slave. 46 Check out example 7 for a similar configuration. 47 48 For multi-chip module MT7530: 49 50 - Port 5 can be used as a CPU port. 51 52 - PHY 0 or 4 of the switch can be muxed to connect to gmac1 of the SoC. 53 Usually used for connecting the wan port directly to the CPU to achieve 2 54 Gbps routing in total. 55 56 The driver looks up the reg on the ethernet-phy node which the phy-handle 57 property refers to on the gmac node to mux the specified phy. 58 59 For the MT7621 SoCs, rgmii2 group must be claimed with rgmii2 function. 60 Check out example 5. 61 62 - In case of an external phy wired to gmac1 of the SoC, port 5 must not be 63 enabled. 64 65 In case of muxing PHY 0 or 4, the external phy must not be enabled. 66 67 For the MT7621 SoCs, rgmii2 group must be claimed with rgmii2 function. 68 Check out example 6. 69 70 - Port 5 can be muxed to an external phy. Port 5 becomes a DSA slave. 71 The external phy must be wired TX to TX to gmac1 of the SoC for this to 72 work. Ubiquiti EdgeRouter X SFP is wired this way. 73 74 Muxing PHY 0 or 4 won't work when the external phy is connected TX to TX. 75 76 For the MT7621 SoCs, rgmii2 group must be claimed with gpio function. 77 Check out example 7. 78 79properties: 80 compatible: 81 oneOf: 82 - description: 83 Standalone MT7530 and multi-chip module MT7530 in MT7623AI SoC 84 const: mediatek,mt7530 85 86 - description: 87 Standalone MT7531 88 const: mediatek,mt7531 89 90 - description: 91 Multi-chip module MT7530 in MT7621AT, MT7621DAT and MT7621ST SoCs 92 const: mediatek,mt7621 93 94 reg: 95 maxItems: 1 96 97 core-supply: 98 description: 99 Phandle to the regulator node necessary for the core power. 100 101 "#gpio-cells": 102 const: 2 103 104 gpio-controller: 105 type: boolean 106 description: 107 If defined, MT7530's LED controller will run on GPIO mode. 108 109 "#interrupt-cells": 110 const: 1 111 112 interrupt-controller: true 113 114 interrupts: 115 maxItems: 1 116 117 io-supply: 118 description: 119 Phandle to the regulator node necessary for the I/O power. 120 See Documentation/devicetree/bindings/regulator/mt6323-regulator.txt for 121 details for the regulator setup on these boards. 122 123 mediatek,mcm: 124 type: boolean 125 description: 126 Used for MT7621AT, MT7621DAT, MT7621ST and MT7623AI SoCs which the MT7530 127 switch is a part of the multi-chip module. 128 129 reset-gpios: 130 description: 131 GPIO to reset the switch. Use this if mediatek,mcm is not used. 132 This property is optional because some boards share the reset line with 133 other components which makes it impossible to probe the switch if the 134 reset line is used. 135 maxItems: 1 136 137 reset-names: 138 const: mcm 139 140 resets: 141 description: 142 Phandle pointing to the system reset controller with line index for the 143 ethsys. 144 maxItems: 1 145 146patternProperties: 147 "^(ethernet-)?ports$": 148 type: object 149 150 patternProperties: 151 "^(ethernet-)?port@[0-9]+$": 152 type: object 153 description: Ethernet switch ports 154 155 unevaluatedProperties: false 156 157 properties: 158 reg: 159 description: 160 Port address described must be 5 or 6 for CPU port and from 0 to 5 161 for user ports. 162 163 allOf: 164 - $ref: dsa-port.yaml# 165 - if: 166 required: [ ethernet ] 167 then: 168 properties: 169 reg: 170 enum: 171 - 5 172 - 6 173 174required: 175 - compatible 176 - reg 177 178$defs: 179 mt7530-dsa-port: 180 patternProperties: 181 "^(ethernet-)?ports$": 182 patternProperties: 183 "^(ethernet-)?port@[0-9]+$": 184 if: 185 required: [ ethernet ] 186 then: 187 if: 188 properties: 189 reg: 190 const: 5 191 then: 192 properties: 193 phy-mode: 194 enum: 195 - gmii 196 - mii 197 - rgmii 198 else: 199 properties: 200 phy-mode: 201 enum: 202 - rgmii 203 - trgmii 204 205 mt7531-dsa-port: 206 patternProperties: 207 "^(ethernet-)?ports$": 208 patternProperties: 209 "^(ethernet-)?port@[0-9]+$": 210 if: 211 required: [ ethernet ] 212 then: 213 if: 214 properties: 215 reg: 216 const: 5 217 then: 218 properties: 219 phy-mode: 220 enum: 221 - 1000base-x 222 - 2500base-x 223 - rgmii 224 - sgmii 225 else: 226 properties: 227 phy-mode: 228 enum: 229 - 1000base-x 230 - 2500base-x 231 - sgmii 232 233allOf: 234 - $ref: dsa.yaml# 235 - if: 236 required: 237 - mediatek,mcm 238 then: 239 properties: 240 reset-gpios: false 241 242 required: 243 - resets 244 - reset-names 245 246 - dependencies: 247 interrupt-controller: [ interrupts ] 248 249 - if: 250 properties: 251 compatible: 252 const: mediatek,mt7530 253 then: 254 $ref: "#/$defs/mt7530-dsa-port" 255 required: 256 - core-supply 257 - io-supply 258 259 - if: 260 properties: 261 compatible: 262 const: mediatek,mt7531 263 then: 264 $ref: "#/$defs/mt7531-dsa-port" 265 properties: 266 mediatek,mcm: false 267 268 - if: 269 properties: 270 compatible: 271 const: mediatek,mt7621 272 then: 273 $ref: "#/$defs/mt7530-dsa-port" 274 required: 275 - mediatek,mcm 276 277unevaluatedProperties: false 278 279examples: 280 # Example 1: Standalone MT7530 281 - | 282 #include <dt-bindings/gpio/gpio.h> 283 284 mdio { 285 #address-cells = <1>; 286 #size-cells = <0>; 287 288 switch@0 { 289 compatible = "mediatek,mt7530"; 290 reg = <0>; 291 292 reset-gpios = <&pio 33 0>; 293 294 core-supply = <&mt6323_vpa_reg>; 295 io-supply = <&mt6323_vemc3v3_reg>; 296 297 ethernet-ports { 298 #address-cells = <1>; 299 #size-cells = <0>; 300 301 port@0 { 302 reg = <0>; 303 label = "lan1"; 304 }; 305 306 port@1 { 307 reg = <1>; 308 label = "lan2"; 309 }; 310 311 port@2 { 312 reg = <2>; 313 label = "lan3"; 314 }; 315 316 port@3 { 317 reg = <3>; 318 label = "lan4"; 319 }; 320 321 port@4 { 322 reg = <4>; 323 label = "wan"; 324 }; 325 326 port@6 { 327 reg = <6>; 328 ethernet = <&gmac0>; 329 phy-mode = "rgmii"; 330 331 fixed-link { 332 speed = <1000>; 333 full-duplex; 334 pause; 335 }; 336 }; 337 }; 338 }; 339 }; 340 341 # Example 2: MT7530 in MT7623AI SoC 342 - | 343 #include <dt-bindings/reset/mt2701-resets.h> 344 345 mdio { 346 #address-cells = <1>; 347 #size-cells = <0>; 348 349 switch@0 { 350 compatible = "mediatek,mt7530"; 351 reg = <0>; 352 353 mediatek,mcm; 354 resets = <ðsys MT2701_ETHSYS_MCM_RST>; 355 reset-names = "mcm"; 356 357 core-supply = <&mt6323_vpa_reg>; 358 io-supply = <&mt6323_vemc3v3_reg>; 359 360 ethernet-ports { 361 #address-cells = <1>; 362 #size-cells = <0>; 363 364 port@0 { 365 reg = <0>; 366 label = "lan1"; 367 }; 368 369 port@1 { 370 reg = <1>; 371 label = "lan2"; 372 }; 373 374 port@2 { 375 reg = <2>; 376 label = "lan3"; 377 }; 378 379 port@3 { 380 reg = <3>; 381 label = "lan4"; 382 }; 383 384 port@4 { 385 reg = <4>; 386 label = "wan"; 387 }; 388 389 port@6 { 390 reg = <6>; 391 ethernet = <&gmac0>; 392 phy-mode = "trgmii"; 393 394 fixed-link { 395 speed = <1000>; 396 full-duplex; 397 pause; 398 }; 399 }; 400 }; 401 }; 402 }; 403 404 # Example 3: Standalone MT7531 405 - | 406 #include <dt-bindings/gpio/gpio.h> 407 #include <dt-bindings/interrupt-controller/irq.h> 408 409 mdio { 410 #address-cells = <1>; 411 #size-cells = <0>; 412 413 switch@0 { 414 compatible = "mediatek,mt7531"; 415 reg = <0>; 416 417 reset-gpios = <&pio 54 0>; 418 419 interrupt-controller; 420 #interrupt-cells = <1>; 421 interrupt-parent = <&pio>; 422 interrupts = <53 IRQ_TYPE_LEVEL_HIGH>; 423 424 ethernet-ports { 425 #address-cells = <1>; 426 #size-cells = <0>; 427 428 port@0 { 429 reg = <0>; 430 label = "lan1"; 431 }; 432 433 port@1 { 434 reg = <1>; 435 label = "lan2"; 436 }; 437 438 port@2 { 439 reg = <2>; 440 label = "lan3"; 441 }; 442 443 port@3 { 444 reg = <3>; 445 label = "lan4"; 446 }; 447 448 port@4 { 449 reg = <4>; 450 label = "wan"; 451 }; 452 453 port@6 { 454 reg = <6>; 455 ethernet = <&gmac0>; 456 phy-mode = "2500base-x"; 457 458 fixed-link { 459 speed = <2500>; 460 full-duplex; 461 pause; 462 }; 463 }; 464 }; 465 }; 466 }; 467 468 # Example 4: MT7530 in MT7621AT, MT7621DAT and MT7621ST SoCs 469 - | 470 #include <dt-bindings/interrupt-controller/mips-gic.h> 471 #include <dt-bindings/reset/mt7621-reset.h> 472 473 mdio { 474 #address-cells = <1>; 475 #size-cells = <0>; 476 477 switch@0 { 478 compatible = "mediatek,mt7621"; 479 reg = <0>; 480 481 mediatek,mcm; 482 resets = <&sysc MT7621_RST_MCM>; 483 reset-names = "mcm"; 484 485 interrupt-controller; 486 #interrupt-cells = <1>; 487 interrupt-parent = <&gic>; 488 interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>; 489 490 ethernet-ports { 491 #address-cells = <1>; 492 #size-cells = <0>; 493 494 port@0 { 495 reg = <0>; 496 label = "lan1"; 497 }; 498 499 port@1 { 500 reg = <1>; 501 label = "lan2"; 502 }; 503 504 port@2 { 505 reg = <2>; 506 label = "lan3"; 507 }; 508 509 port@3 { 510 reg = <3>; 511 label = "lan4"; 512 }; 513 514 port@4 { 515 reg = <4>; 516 label = "wan"; 517 }; 518 519 port@6 { 520 reg = <6>; 521 ethernet = <&gmac0>; 522 phy-mode = "trgmii"; 523 524 fixed-link { 525 speed = <1000>; 526 full-duplex; 527 pause; 528 }; 529 }; 530 }; 531 }; 532 }; 533 534 # Example 5: MT7621: mux MT7530's phy4 to SoC's gmac1 535 - | 536 #include <dt-bindings/interrupt-controller/mips-gic.h> 537 #include <dt-bindings/reset/mt7621-reset.h> 538 539 ethernet { 540 #address-cells = <1>; 541 #size-cells = <0>; 542 543 pinctrl-names = "default"; 544 pinctrl-0 = <&rgmii2_pins>; 545 546 mac@1 { 547 compatible = "mediatek,eth-mac"; 548 reg = <1>; 549 550 phy-mode = "rgmii"; 551 phy-handle = <&example5_ethphy4>; 552 }; 553 554 mdio { 555 #address-cells = <1>; 556 #size-cells = <0>; 557 558 /* MT7530's phy4 */ 559 example5_ethphy4: ethernet-phy@4 { 560 reg = <4>; 561 }; 562 563 switch@0 { 564 compatible = "mediatek,mt7621"; 565 reg = <0>; 566 567 mediatek,mcm; 568 resets = <&sysc MT7621_RST_MCM>; 569 reset-names = "mcm"; 570 571 interrupt-controller; 572 #interrupt-cells = <1>; 573 interrupt-parent = <&gic>; 574 interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>; 575 576 ethernet-ports { 577 #address-cells = <1>; 578 #size-cells = <0>; 579 580 port@0 { 581 reg = <0>; 582 label = "lan1"; 583 }; 584 585 port@1 { 586 reg = <1>; 587 label = "lan2"; 588 }; 589 590 port@2 { 591 reg = <2>; 592 label = "lan3"; 593 }; 594 595 port@3 { 596 reg = <3>; 597 label = "lan4"; 598 }; 599 600 /* Commented out, phy4 is muxed to gmac1. 601 port@4 { 602 reg = <4>; 603 label = "wan"; 604 }; 605 */ 606 607 port@6 { 608 reg = <6>; 609 ethernet = <&gmac0>; 610 phy-mode = "trgmii"; 611 612 fixed-link { 613 speed = <1000>; 614 full-duplex; 615 pause; 616 }; 617 }; 618 }; 619 }; 620 }; 621 }; 622 623 # Example 6: MT7621: mux external phy to SoC's gmac1 624 - | 625 #include <dt-bindings/interrupt-controller/mips-gic.h> 626 #include <dt-bindings/reset/mt7621-reset.h> 627 628 ethernet { 629 #address-cells = <1>; 630 #size-cells = <0>; 631 632 pinctrl-names = "default"; 633 pinctrl-0 = <&rgmii2_pins>; 634 635 mac@1 { 636 compatible = "mediatek,eth-mac"; 637 reg = <1>; 638 639 phy-mode = "rgmii"; 640 phy-handle = <&example6_ethphy7>; 641 }; 642 643 mdio { 644 #address-cells = <1>; 645 #size-cells = <0>; 646 647 /* External PHY */ 648 example6_ethphy7: ethernet-phy@7 { 649 reg = <7>; 650 phy-mode = "rgmii"; 651 }; 652 653 switch@0 { 654 compatible = "mediatek,mt7621"; 655 reg = <0>; 656 657 mediatek,mcm; 658 resets = <&sysc MT7621_RST_MCM>; 659 reset-names = "mcm"; 660 661 interrupt-controller; 662 #interrupt-cells = <1>; 663 interrupt-parent = <&gic>; 664 interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>; 665 666 ethernet-ports { 667 #address-cells = <1>; 668 #size-cells = <0>; 669 670 port@0 { 671 reg = <0>; 672 label = "lan1"; 673 }; 674 675 port@1 { 676 reg = <1>; 677 label = "lan2"; 678 }; 679 680 port@2 { 681 reg = <2>; 682 label = "lan3"; 683 }; 684 685 port@3 { 686 reg = <3>; 687 label = "lan4"; 688 }; 689 690 port@4 { 691 reg = <4>; 692 label = "wan"; 693 }; 694 695 port@6 { 696 reg = <6>; 697 ethernet = <&gmac0>; 698 phy-mode = "trgmii"; 699 700 fixed-link { 701 speed = <1000>; 702 full-duplex; 703 pause; 704 }; 705 }; 706 }; 707 }; 708 }; 709 }; 710 711 # Example 7: MT7621: mux external phy to MT7530's port 5 712 - | 713 #include <dt-bindings/interrupt-controller/mips-gic.h> 714 #include <dt-bindings/reset/mt7621-reset.h> 715 716 ethernet { 717 #address-cells = <1>; 718 #size-cells = <0>; 719 720 pinctrl-names = "default"; 721 pinctrl-0 = <&rgmii2_pins>; 722 723 mdio { 724 #address-cells = <1>; 725 #size-cells = <0>; 726 727 /* External PHY */ 728 example7_ethphy7: ethernet-phy@7 { 729 reg = <7>; 730 phy-mode = "rgmii"; 731 }; 732 733 switch@0 { 734 compatible = "mediatek,mt7621"; 735 reg = <0>; 736 737 mediatek,mcm; 738 resets = <&sysc MT7621_RST_MCM>; 739 reset-names = "mcm"; 740 741 interrupt-controller; 742 #interrupt-cells = <1>; 743 interrupt-parent = <&gic>; 744 interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>; 745 746 ethernet-ports { 747 #address-cells = <1>; 748 #size-cells = <0>; 749 750 port@0 { 751 reg = <0>; 752 label = "lan1"; 753 }; 754 755 port@1 { 756 reg = <1>; 757 label = "lan2"; 758 }; 759 760 port@2 { 761 reg = <2>; 762 label = "lan3"; 763 }; 764 765 port@3 { 766 reg = <3>; 767 label = "lan4"; 768 }; 769 770 port@4 { 771 reg = <4>; 772 label = "wan"; 773 }; 774 775 port@5 { 776 reg = <5>; 777 label = "extphy"; 778 phy-mode = "rgmii-txid"; 779 phy-handle = <&example7_ethphy7>; 780 }; 781 782 port@6 { 783 reg = <6>; 784 ethernet = <&gmac0>; 785 phy-mode = "trgmii"; 786 787 fixed-link { 788 speed = <1000>; 789 full-duplex; 790 pause; 791 }; 792 }; 793 }; 794 }; 795 }; 796 }; 797