1Marvell Distributed Switch Architecture Device Tree Bindings 2------------------------------------------------------------ 3 4Required properties: 5- compatible : Should be "marvell,dsa" 6- #address-cells : Must be 2, first cell is the address on the MDIO bus 7 and second cell is the address in the switch tree. 8 Second cell is used only when cascading/chaining. 9- #size-cells : Must be 0 10- dsa,ethernet : Should be a phandle to a valid Ethernet device node 11- dsa,mii-bus : Should be a phandle to a valid MDIO bus device node 12 13Optionnal properties: 14- interrupts : property with a value describing the switch 15 interrupt number (not supported by the driver) 16 17A DSA node can contain multiple switch chips which are therefore child nodes of 18the parent DSA node. The maximum number of allowed child nodes is 4 19(DSA_MAX_SWITCHES). 20Each of these switch child nodes should have the following required properties: 21 22- reg : Describes the switch address on the MII bus 23- #address-cells : Must be 1 24- #size-cells : Must be 0 25 26A switch may have multiple "port" children nodes 27 28Each port children node must have the following mandatory properties: 29- reg : Describes the port address in the switch 30- label : Describes the label associated with this port, special 31 labels are "cpu" to indicate a CPU port and "dsa" to 32 indicate an uplink/downlink port. 33 34Note that a port labelled "dsa" will imply checking for the uplink phandle 35described below. 36 37Optionnal property: 38- link : Should be a phandle to another switch's DSA port. 39 This property is only used when switches are being 40 chained/cascaded together. 41 42Example: 43 44 dsa@0 { 45 compatible = "marvell,dsa"; 46 #address-cells = <2>; 47 #size-cells = <0>; 48 49 interrupts = <10>; 50 dsa,ethernet = <ðernet0>; 51 dsa,mii-bus = <&mii_bus0>; 52 53 switch@0 { 54 #address-cells = <1>; 55 #size-cells = <0>; 56 reg = <16 0>; /* MDIO address 16, switch 0 in tree */ 57 58 port@0 { 59 reg = <0>; 60 label = "lan1"; 61 }; 62 63 port@1 { 64 reg = <1>; 65 label = "lan2"; 66 }; 67 68 port@5 { 69 reg = <5>; 70 label = "cpu"; 71 }; 72 73 switch0uplink: port@6 { 74 reg = <6>; 75 label = "dsa"; 76 link = <&switch1uplink>; 77 }; 78 }; 79 80 switch@1 { 81 #address-cells = <1>; 82 #size-cells = <0>; 83 reg = <17 1>; /* MDIO address 17, switch 1 in tree */ 84 85 switch1uplink: port@0 { 86 reg = <0>; 87 label = "dsa"; 88 link = <&switch0uplink>; 89 }; 90 }; 91 }; 92