1Marvell Distributed Switch Architecture Device Tree Bindings
2------------------------------------------------------------
3
4Required properties:
5- compatible		: Should be "marvell,dsa"
6- #address-cells	: Must be 2, first cell is the address on the MDIO bus
7			  and second cell is the address in the switch tree.
8			  Second cell is used only when cascading/chaining.
9- #size-cells		: Must be 0
10- dsa,ethernet		: Should be a phandle to a valid Ethernet device node
11- dsa,mii-bus		: Should be a phandle to a valid MDIO bus device node
12
13Optional properties:
14- interrupts		: property with a value describing the switch
15			  interrupt number (not supported by the driver)
16
17A DSA node can contain multiple switch chips which are therefore child nodes of
18the parent DSA node. The maximum number of allowed child nodes is 4
19(DSA_MAX_SWITCHES).
20Each of these switch child nodes should have the following required properties:
21
22- reg			: Contains two fields. The first one describes the
23			  address on the MII bus. The second is the switch
24			  number that must be unique in cascaded configurations
25- #address-cells	: Must be 1
26- #size-cells		: Must be 0
27
28A switch child node has the following optional property:
29
30- eeprom-length		: Set to the length of an EEPROM connected to the
31			  switch. Must be set if the switch can not detect
32			  the presence and/or size of a connected EEPROM,
33			  otherwise optional.
34- reset-gpios		: phandle and specifier to a gpio line connected to
35			  reset pin of the switch chip.
36
37A switch may have multiple "port" children nodes
38
39Each port children node must have the following mandatory properties:
40- reg			: Describes the port address in the switch
41- label			: Describes the label associated with this port, special
42			  labels are "cpu" to indicate a CPU port and "dsa" to
43			  indicate an uplink/downlink port.
44
45Note that a port labelled "dsa" will imply checking for the uplink phandle
46described below.
47
48Optionnal property:
49- link			: Should be a list of phandles to another switch's DSA port.
50			  This property is only used when switches are being
51			  chained/cascaded together. This port is used as outgoing port
52			  towards the phandle port, which can be more than one hop away.
53
54- phy-handle		: Phandle to a PHY on an external MDIO bus, not the
55			  switch internal one. See
56			  Documentation/devicetree/bindings/net/ethernet.txt
57			  for details.
58
59- phy-mode		: String representing the connection to the designated
60			  PHY node specified by the 'phy-handle' property. See
61			  Documentation/devicetree/bindings/net/ethernet.txt
62			  for details.
63
64- mii-bus		: Should be a phandle to a valid MDIO bus device node.
65			  This mii-bus will be used in preference to the
66			  global dsa,mii-bus defined above, for this switch.
67
68Optional subnodes:
69- fixed-link		: Fixed-link subnode describing a link to a non-MDIO
70			  managed entity. See
71			  Documentation/devicetree/bindings/net/fixed-link.txt
72			  for details.
73
74Example:
75
76	dsa@0 {
77		compatible = "marvell,dsa";
78		#address-cells = <2>;
79		#size-cells = <0>;
80
81		interrupts = <10>;
82		dsa,ethernet = <&ethernet0>;
83		dsa,mii-bus = <&mii_bus0>;
84
85		switch@0 {
86			#address-cells = <1>;
87			#size-cells = <0>;
88			reg = <16 0>;	/* MDIO address 16, switch 0 in tree */
89
90			port@0 {
91				reg = <0>;
92				label = "lan1";
93				phy-handle = <&phy0>;
94			};
95
96			port@1 {
97				reg = <1>;
98				label = "lan2";
99			};
100
101			port@5 {
102				reg = <5>;
103				label = "cpu";
104			};
105
106			switch0port6: port@6 {
107				reg = <6>;
108				label = "dsa";
109				link = <&switch1port0
110				        &switch2port0>;
111			};
112		};
113
114		switch@1 {
115			#address-cells = <1>;
116			#size-cells = <0>;
117			reg = <17 1>;	/* MDIO address 17, switch 1 in tree */
118			mii-bus = <&mii_bus1>;
119			reset-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
120
121			switch1port0: port@0 {
122				reg = <0>;
123				label = "dsa";
124				link = <&switch0port6>;
125			};
126			switch1port1: port@1 {
127				reg = <1>;
128				label = "dsa";
129				link = <&switch2port1>;
130			};
131		};
132
133		switch@2 {
134			#address-cells = <1>;
135			#size-cells = <0>;
136			reg = <18 2>;	/* MDIO address 18, switch 2 in tree */
137			mii-bus = <&mii_bus1>;
138
139			switch2port0: port@0 {
140				reg = <0>;
141				label = "dsa";
142				link = <&switch1port1
143				        &switch0port6>;
144			};
145		};
146	};
147