1Marvell Distributed Switch Architecture Device Tree Bindings
2------------------------------------------------------------
3
4Required properties:
5- compatible		: Should be "marvell,dsa"
6- #address-cells	: Must be 2, first cell is the address on the MDIO bus
7			  and second cell is the address in the switch tree.
8			  Second cell is used only when cascading/chaining.
9- #size-cells		: Must be 0
10- dsa,ethernet		: Should be a phandle to a valid Ethernet device node
11- dsa,mii-bus		: Should be a phandle to a valid MDIO bus device node
12
13Optional properties:
14- interrupts		: property with a value describing the switch
15			  interrupt number (not supported by the driver)
16
17A DSA node can contain multiple switch chips which are therefore child nodes of
18the parent DSA node. The maximum number of allowed child nodes is 4
19(DSA_MAX_SWITCHES).
20Each of these switch child nodes should have the following required properties:
21
22- reg			: Contains two fields. The first one describes the
23			  address on the MII bus. The second is the switch
24			  number that must be unique in cascaded configurations
25- #address-cells	: Must be 1
26- #size-cells		: Must be 0
27
28A switch child node has the following optional property:
29
30- eeprom-length		: Set to the length of an EEPROM connected to the
31			  switch. Must be set if the switch can not detect
32			  the presence and/or size of a connected EEPROM,
33			  otherwise optional.
34
35A switch may have multiple "port" children nodes
36
37Each port children node must have the following mandatory properties:
38- reg			: Describes the port address in the switch
39- label			: Describes the label associated with this port, special
40			  labels are "cpu" to indicate a CPU port and "dsa" to
41			  indicate an uplink/downlink port.
42
43Note that a port labelled "dsa" will imply checking for the uplink phandle
44described below.
45
46Optionnal property:
47- link			: Should be a list of phandles to another switch's DSA port.
48			  This property is only used when switches are being
49			  chained/cascaded together. This port is used as outgoing port
50			  towards the phandle port, which can be more than one hop away.
51
52- phy-handle		: Phandle to a PHY on an external MDIO bus, not the
53			  switch internal one. See
54			  Documentation/devicetree/bindings/net/ethernet.txt
55			  for details.
56
57- phy-mode		: String representing the connection to the designated
58			  PHY node specified by the 'phy-handle' property. See
59			  Documentation/devicetree/bindings/net/ethernet.txt
60			  for details.
61
62- mii-bus		: Should be a phandle to a valid MDIO bus device node.
63			  This mii-bus will be used in preference to the
64			  global dsa,mii-bus defined above, for this switch.
65
66Optional subnodes:
67- fixed-link		: Fixed-link subnode describing a link to a non-MDIO
68			  managed entity. See
69			  Documentation/devicetree/bindings/net/fixed-link.txt
70			  for details.
71
72Example:
73
74	dsa@0 {
75		compatible = "marvell,dsa";
76		#address-cells = <2>;
77		#size-cells = <0>;
78
79		interrupts = <10>;
80		dsa,ethernet = <&ethernet0>;
81		dsa,mii-bus = <&mii_bus0>;
82
83		switch@0 {
84			#address-cells = <1>;
85			#size-cells = <0>;
86			reg = <16 0>;	/* MDIO address 16, switch 0 in tree */
87
88			port@0 {
89				reg = <0>;
90				label = "lan1";
91				phy-handle = <&phy0>;
92			};
93
94			port@1 {
95				reg = <1>;
96				label = "lan2";
97			};
98
99			port@5 {
100				reg = <5>;
101				label = "cpu";
102			};
103
104			switch0port6: port@6 {
105				reg = <6>;
106				label = "dsa";
107				link = <&switch1port0
108				        &switch2port0>;
109			};
110		};
111
112		switch@1 {
113			#address-cells = <1>;
114			#size-cells = <0>;
115			reg = <17 1>;	/* MDIO address 17, switch 1 in tree */
116			mii-bus = <&mii_bus1>;
117			reset-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
118
119			switch1port0: port@0 {
120				reg = <0>;
121				label = "dsa";
122				link = <&switch0port6>;
123			};
124			switch1port1: port@1 {
125				reg = <1>;
126				label = "dsa";
127				link = <&switch2port1>;
128			};
129		};
130
131		switch@2 {
132			#address-cells = <1>;
133			#size-cells = <0>;
134			reg = <18 2>;	/* MDIO address 18, switch 2 in tree */
135			mii-bus = <&mii_bus1>;
136
137			switch2port0: port@0 {
138				reg = <0>;
139				label = "dsa";
140				link = <&switch1port1
141				        &switch0port6>;
142			};
143		};
144	};
145