1Distributed Switch Architecture Device Tree Bindings
2----------------------------------------------------
3
4Two bindings exist, one of which has been deprecated due to
5limitations.
6
7Current Binding
8---------------
9
10Switches are true Linux devices and can be probed by any means. Once
11probed, they register to the DSA framework, passing a node
12pointer. This node is expected to fulfil the following binding, and
13may contain additional properties as required by the device it is
14embedded within.
15
16Required properties:
17
18- ports		: A container for child nodes representing switch ports.
19
20Optional properties:
21
22- dsa,member	: A two element list indicates which DSA cluster, and position
23		  within the cluster a switch takes. <0 0> is cluster 0,
24		  switch 0. <0 1> is cluster 0, switch 1. <1 0> is cluster 1,
25		  switch 0. A switch not part of any cluster (single device
26		  hanging off a CPU port) must not specify this property
27
28The ports container has the following properties
29
30Required properties:
31
32- #address-cells	: Must be 1
33- #size-cells		: Must be 0
34
35Each port children node must have the following mandatory properties:
36- reg			: Describes the port address in the switch
37
38An uplink/downlink port between switches in the cluster has the following
39mandatory property:
40
41- link			: Should be a list of phandles to other switch's DSA
42			  port. This port is used as the outgoing port
43			  towards the phandle ports. The full routing
44			  information must be given, not just the one hop
45			  routes to neighbouring switches.
46
47A CPU port has the following mandatory property:
48
49- ethernet		: Should be a phandle to a valid Ethernet device node.
50                          This host device is what the switch port is
51			  connected to.
52
53A user port has the following optional property:
54
55- label			: Describes the label associated with this port, which
56                          will become the netdev name.
57
58Port child nodes may also contain the following optional standardised
59properties, described in binding documents:
60
61- phy-handle		: Phandle to a PHY on an MDIO bus. See
62			  Documentation/devicetree/bindings/net/ethernet.txt
63			  for details.
64
65- phy-mode		: See
66			  Documentation/devicetree/bindings/net/ethernet.txt
67			  for details.
68
69- fixed-link		: Fixed-link subnode describing a link to a non-MDIO
70			  managed entity. See
71			  Documentation/devicetree/bindings/net/fixed-link.txt
72			  for details.
73
74- local-mac-address	: See
75			  Documentation/devicetree/bindings/net/ethernet.txt
76			  for details.
77
78Example
79
80The following example shows three switches on three MDIO busses,
81linked into one DSA cluster.
82
83&mdio1 {
84	#address-cells = <1>;
85	#size-cells = <0>;
86
87	switch0: switch0@0 {
88		compatible = "marvell,mv88e6085";
89		reg = <0>;
90
91		dsa,member = <0 0>;
92
93		ports {
94			#address-cells = <1>;
95			#size-cells = <0>;
96			port@0 {
97				reg = <0>;
98				label = "lan0";
99			};
100
101			port@1 {
102				reg = <1>;
103				label = "lan1";
104				local-mac-address = [00 00 00 00 00 00];
105			};
106
107			port@2 {
108				reg = <2>;
109				label = "lan2";
110			};
111
112			switch0port5: port@5 {
113				reg = <5>;
114				phy-mode = "rgmii-txid";
115				link = <&switch1port6
116					&switch2port9>;
117				fixed-link {
118					speed = <1000>;
119					full-duplex;
120				};
121			};
122
123			port@6 {
124				reg = <6>;
125				ethernet = <&fec1>;
126				fixed-link {
127					speed = <100>;
128					full-duplex;
129				};
130			};
131		};
132	};
133};
134
135&mdio2 {
136	#address-cells = <1>;
137	#size-cells = <0>;
138
139	switch1: switch1@0 {
140		compatible = "marvell,mv88e6085";
141		reg = <0>;
142
143		dsa,member = <0 1>;
144
145		ports {
146			#address-cells = <1>;
147			#size-cells = <0>;
148			port@0 {
149				reg = <0>;
150				label = "lan3";
151				phy-handle = <&switch1phy0>;
152			};
153
154			port@1 {
155				reg = <1>;
156				label = "lan4";
157				phy-handle = <&switch1phy1>;
158			};
159
160			port@2 {
161				reg = <2>;
162				label = "lan5";
163				phy-handle = <&switch1phy2>;
164			};
165
166			switch1port5: port@5 {
167				reg = <5>;
168				link = <&switch2port9>;
169				phy-mode = "rgmii-txid";
170				fixed-link {
171					speed = <1000>;
172					full-duplex;
173				};
174			};
175
176			switch1port6: port@6 {
177				reg = <6>;
178				phy-mode = "rgmii-txid";
179				link = <&switch0port5>;
180				fixed-link {
181					speed = <1000>;
182					full-duplex;
183				};
184			};
185		};
186		mdio-bus {
187			#address-cells = <1>;
188			#size-cells = <0>;
189			switch1phy0: switch1phy0@0 {
190				reg = <0>;
191			};
192			switch1phy1: switch1phy0@1 {
193				reg = <1>;
194			};
195			switch1phy2: switch1phy0@2 {
196				reg = <2>;
197			};
198		};
199	 };
200};
201
202&mdio4 {
203	#address-cells = <1>;
204	#size-cells = <0>;
205
206	switch2: switch2@0 {
207		compatible = "marvell,mv88e6085";
208		reg = <0>;
209
210		dsa,member = <0 2>;
211
212		ports {
213			#address-cells = <1>;
214			#size-cells = <0>;
215			port@0 {
216				reg = <0>;
217				label = "lan6";
218			};
219
220			port@1 {
221				reg = <1>;
222				label = "lan7";
223			};
224
225			port@2 {
226				reg = <2>;
227				label = "lan8";
228			};
229
230			port@3 {
231				reg = <3>;
232				label = "optical3";
233				fixed-link {
234					speed = <1000>;
235					full-duplex;
236					link-gpios = <&gpio6 2
237					      GPIO_ACTIVE_HIGH>;
238				};
239			};
240
241			port@4 {
242				reg = <4>;
243				label = "optical4";
244				fixed-link {
245					speed = <1000>;
246					full-duplex;
247					link-gpios = <&gpio6 3
248					      GPIO_ACTIVE_HIGH>;
249				};
250			};
251
252			switch2port9: port@9 {
253				reg = <9>;
254				phy-mode = "rgmii-txid";
255				link = <&switch1port5
256					&switch0port5>;
257				fixed-link {
258					speed = <1000>;
259					full-duplex;
260				};
261			};
262		};
263	};
264};
265
266Deprecated Binding
267------------------
268
269The deprecated binding makes use of a platform device to represent the
270switches. The switches themselves are not Linux devices, and make use
271of an MDIO bus for management.
272
273Required properties:
274- compatible		: Should be "marvell,dsa"
275- #address-cells	: Must be 2, first cell is the address on the MDIO bus
276			  and second cell is the address in the switch tree.
277			  Second cell is used only when cascading/chaining.
278- #size-cells		: Must be 0
279- dsa,ethernet		: Should be a phandle to a valid Ethernet device node
280- dsa,mii-bus		: Should be a phandle to a valid MDIO bus device node
281
282Optional properties:
283- interrupts		: property with a value describing the switch
284			  interrupt number (not supported by the driver)
285
286A DSA node can contain multiple switch chips which are therefore child nodes of
287the parent DSA node. The maximum number of allowed child nodes is 4
288(DSA_MAX_SWITCHES).
289Each of these switch child nodes should have the following required properties:
290
291- reg			: Contains two fields. The first one describes the
292			  address on the MII bus. The second is the switch
293			  number that must be unique in cascaded configurations
294- #address-cells	: Must be 1
295- #size-cells		: Must be 0
296
297A switch child node has the following optional property:
298
299- eeprom-length		: Set to the length of an EEPROM connected to the
300			  switch. Must be set if the switch can not detect
301			  the presence and/or size of a connected EEPROM,
302			  otherwise optional.
303
304A switch may have multiple "port" children nodes
305
306Each port children node must have the following mandatory properties:
307- reg			: Describes the port address in the switch
308- label			: Describes the label associated with this port, special
309			  labels are "cpu" to indicate a CPU port and "dsa" to
310			  indicate an uplink/downlink port.
311
312Note that a port labelled "dsa" will imply checking for the uplink phandle
313described below.
314
315Optional property:
316- link			: Should be a list of phandles to another switch's DSA port.
317			  This property is only used when switches are being
318			  chained/cascaded together. This port is used as outgoing port
319			  towards the phandle port, which can be more than one hop away.
320
321- phy-handle		: Phandle to a PHY on an external MDIO bus, not the
322			  switch internal one. See
323			  Documentation/devicetree/bindings/net/ethernet.txt
324			  for details.
325
326- phy-mode		: String representing the connection to the designated
327			  PHY node specified by the 'phy-handle' property. See
328			  Documentation/devicetree/bindings/net/ethernet.txt
329			  for details.
330
331- mii-bus		: Should be a phandle to a valid MDIO bus device node.
332			  This mii-bus will be used in preference to the
333			  global dsa,mii-bus defined above, for this switch.
334
335Optional subnodes:
336- fixed-link		: Fixed-link subnode describing a link to a non-MDIO
337			  managed entity. See
338			  Documentation/devicetree/bindings/net/fixed-link.txt
339			  for details.
340
341Example:
342
343	dsa@0 {
344		compatible = "marvell,dsa";
345		#address-cells = <2>;
346		#size-cells = <0>;
347
348		interrupts = <10>;
349		dsa,ethernet = <&ethernet0>;
350		dsa,mii-bus = <&mii_bus0>;
351
352		switch@0 {
353			#address-cells = <1>;
354			#size-cells = <0>;
355			reg = <16 0>;	/* MDIO address 16, switch 0 in tree */
356
357			port@0 {
358				reg = <0>;
359				label = "lan1";
360				phy-handle = <&phy0>;
361			};
362
363			port@1 {
364				reg = <1>;
365				label = "lan2";
366			};
367
368			port@5 {
369				reg = <5>;
370				label = "cpu";
371			};
372
373			switch0port6: port@6 {
374				reg = <6>;
375				label = "dsa";
376				link = <&switch1port0
377				        &switch2port0>;
378			};
379		};
380
381		switch@1 {
382			#address-cells = <1>;
383			#size-cells = <0>;
384			reg = <17 1>;	/* MDIO address 17, switch 1 in tree */
385			mii-bus = <&mii_bus1>;
386			reset-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
387
388			switch1port0: port@0 {
389				reg = <0>;
390				label = "dsa";
391				link = <&switch0port6>;
392			};
393			switch1port1: port@1 {
394				reg = <1>;
395				label = "dsa";
396				link = <&switch2port1>;
397			};
398		};
399
400		switch@2 {
401			#address-cells = <1>;
402			#size-cells = <0>;
403			reg = <18 2>;	/* MDIO address 18, switch 2 in tree */
404			mii-bus = <&mii_bus1>;
405
406			switch2port0: port@0 {
407				reg = <0>;
408				label = "dsa";
409				link = <&switch1port1
410				        &switch0port6>;
411			};
412		};
413	};
414