15892cd13SMugunthan V NTI CPSW Phy mode Selection Device Tree Bindings 25892cd13SMugunthan V N----------------------------------------------- 35892cd13SMugunthan V N 45892cd13SMugunthan V NRequired properties: 5d415fa1bSMugunthan V N- compatible : Should be "ti,am3352-cpsw-phy-sel" for am335x platform and 6d415fa1bSMugunthan V N "ti,dra7xx-cpsw-phy-sel" for dra7xx platform 75892cd13SMugunthan V N- reg : physical base address and size of the cpsw 85892cd13SMugunthan V N registers map 95892cd13SMugunthan V N- reg-names : names of the register map given in "reg" node 105892cd13SMugunthan V N 115892cd13SMugunthan V NOptional properties: 125892cd13SMugunthan V N-rmii-clock-ext : If present, the driver will configure the RMII 135892cd13SMugunthan V N interface to external clock usage 145892cd13SMugunthan V N 155892cd13SMugunthan V NExamples: 165892cd13SMugunthan V N 175892cd13SMugunthan V N phy_sel: cpsw-phy-sel@44e10650 { 185892cd13SMugunthan V N compatible = "ti,am3352-cpsw-phy-sel"; 195892cd13SMugunthan V N reg= <0x44e10650 0x4>; 205892cd13SMugunthan V N reg-names = "gmii-sel"; 215892cd13SMugunthan V N }; 225892cd13SMugunthan V N 235892cd13SMugunthan V N(or) 245892cd13SMugunthan V N phy_sel: cpsw-phy-sel@44e10650 { 255892cd13SMugunthan V N compatible = "ti,am3352-cpsw-phy-sel"; 265892cd13SMugunthan V N reg= <0x44e10650 0x4>; 275892cd13SMugunthan V N reg-names = "gmii-sel"; 285892cd13SMugunthan V N rmii-clock-ext; 295892cd13SMugunthan V N }; 30