1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/net/cdns,macb.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Cadence MACB/GEM Ethernet controller 8 9maintainers: 10 - Nicolas Ferre <nicolas.ferre@microchip.com> 11 - Claudiu Beznea <claudiu.beznea@microchip.com> 12 13properties: 14 compatible: 15 oneOf: 16 - items: 17 - enum: 18 - cdns,at91rm9200-emac # Atmel at91rm9200 SoC 19 - const: cdns,emac # Generic 20 21 - items: 22 - enum: 23 - cdns,zynq-gem # Xilinx Zynq-7xxx SoC 24 - cdns,zynqmp-gem # Xilinx Zynq Ultrascale+ MPSoC 25 - const: cdns,gem # Generic 26 deprecated: true 27 28 - items: 29 - enum: 30 - xlnx,versal-gem # Xilinx Versal 31 - xlnx,zynq-gem # Xilinx Zynq-7xxx SoC 32 - xlnx,zynqmp-gem # Xilinx Zynq Ultrascale+ MPSoC 33 - const: cdns,gem # Generic 34 35 - items: 36 - enum: 37 - cdns,at91sam9260-macb # Atmel at91sam9 SoCs 38 - cdns,sam9x60-macb # Microchip sam9x60 SoC 39 - microchip,mpfs-macb # Microchip PolarFire SoC 40 - const: cdns,macb # Generic 41 42 - items: 43 - enum: 44 - atmel,sama5d3-macb # 10/100Mbit IP on Atmel sama5d3 SoCs 45 - enum: 46 - cdns,at91sam9260-macb # Atmel at91sam9 SoCs. 47 - const: cdns,macb # Generic 48 49 - enum: 50 - atmel,sama5d29-gem # GEM XL IP (10/100) on Atmel sama5d29 SoCs 51 - atmel,sama5d2-gem # GEM IP (10/100) on Atmel sama5d2 SoCs 52 - atmel,sama5d3-gem # Gigabit IP on Atmel sama5d3 SoCs 53 - atmel,sama5d4-gem # GEM IP (10/100) on Atmel sama5d4 SoCs 54 - cdns,np4-macb # NP4 SoC devices 55 - microchip,sama7g5-emac # Microchip SAMA7G5 ethernet interface 56 - microchip,sama7g5-gem # Microchip SAMA7G5 gigabit ethernet interface 57 - sifive,fu540-c000-gem # SiFive FU540-C000 SoC 58 - cdns,emac # Generic 59 - cdns,gem # Generic 60 - cdns,macb # Generic 61 62 reg: 63 minItems: 1 64 items: 65 - description: Basic register set 66 - description: GEMGXL Management block registers on SiFive FU540-C000 SoC 67 68 interrupts: 69 minItems: 1 70 maxItems: 8 71 description: One interrupt per available hardware queue 72 73 clocks: 74 minItems: 1 75 maxItems: 5 76 77 clock-names: 78 minItems: 1 79 items: 80 - enum: [ ether_clk, hclk, pclk ] 81 - enum: [ hclk, pclk ] 82 - const: tx_clk 83 - enum: [ rx_clk, tsu_clk ] 84 - const: tsu_clk 85 86 local-mac-address: true 87 88 phy-mode: true 89 90 phy-handle: true 91 92 phys: 93 maxItems: 1 94 95 resets: 96 maxItems: 1 97 description: 98 Recommended with ZynqMP, specify reset control for this 99 controller instance with zynqmp-reset driver. 100 101 reset-names: 102 maxItems: 1 103 104 fixed-link: true 105 106 iommus: 107 maxItems: 1 108 109 power-domains: 110 maxItems: 1 111 112 '#address-cells': 113 const: 1 114 115 '#size-cells': 116 const: 0 117 118 mdio: 119 type: object 120 description: 121 Node containing PHY children. If this node is not present, then PHYs will 122 be direct children. 123 124patternProperties: 125 "^ethernet-phy@[0-9a-f]$": 126 type: object 127 $ref: ethernet-phy.yaml# 128 129 properties: 130 reset-gpios: true 131 132 magic-packet: 133 type: boolean 134 description: 135 Indicates that the hardware supports waking up via magic packet. 136 137 unevaluatedProperties: false 138 139required: 140 - compatible 141 - reg 142 - interrupts 143 - clocks 144 - clock-names 145 - phy-mode 146 147allOf: 148 - $ref: ethernet-controller.yaml# 149 150 - if: 151 not: 152 properties: 153 compatible: 154 contains: 155 const: sifive,fu540-c000-gem 156 then: 157 properties: 158 reg: 159 maxItems: 1 160 161unevaluatedProperties: false 162 163examples: 164 - | 165 macb0: ethernet@fffc4000 { 166 compatible = "cdns,macb"; 167 reg = <0xfffc4000 0x4000>; 168 interrupts = <21>; 169 phy-mode = "rmii"; 170 local-mac-address = [3a 0e 03 04 05 06]; 171 clock-names = "pclk", "hclk", "tx_clk"; 172 clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>; 173 #address-cells = <1>; 174 #size-cells = <0>; 175 176 ethernet-phy@1 { 177 reg = <0x1>; 178 reset-gpios = <&pioE 6 1>; 179 }; 180 }; 181 182 - | 183 #include <dt-bindings/clock/xlnx-zynqmp-clk.h> 184 #include <dt-bindings/power/xlnx-zynqmp-power.h> 185 #include <dt-bindings/reset/xlnx-zynqmp-resets.h> 186 #include <dt-bindings/phy/phy.h> 187 188 bus { 189 #address-cells = <2>; 190 #size-cells = <2>; 191 gem1: ethernet@ff0c0000 { 192 compatible = "xlnx,zynqmp-gem", "cdns,gem"; 193 interrupt-parent = <&gic>; 194 interrupts = <0 59 4>, <0 59 4>; 195 reg = <0x0 0xff0c0000 0x0 0x1000>; 196 clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>, 197 <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>, 198 <&zynqmp_clk GEM_TSU>; 199 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; 200 #address-cells = <1>; 201 #size-cells = <0>; 202 iommus = <&smmu 0x875>; 203 power-domains = <&zynqmp_firmware PD_ETH_1>; 204 resets = <&zynqmp_reset ZYNQMP_RESET_GEM1>; 205 reset-names = "gem1_rst"; 206 status = "okay"; 207 phy-mode = "sgmii"; 208 phys = <&psgtr 1 PHY_TYPE_SGMII 1 1>; 209 fixed-link { 210 speed = <1000>; 211 full-duplex; 212 pause; 213 }; 214 }; 215 }; 216