1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/net/cdns,macb.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Cadence MACB/GEM Ethernet controller 8 9maintainers: 10 - Nicolas Ferre <nicolas.ferre@microchip.com> 11 - Claudiu Beznea <claudiu.beznea@microchip.com> 12 13properties: 14 compatible: 15 oneOf: 16 - items: 17 - enum: 18 - cdns,at91rm9200-emac # Atmel at91rm9200 SoC 19 - const: cdns,emac # Generic 20 21 - items: 22 - enum: 23 - cdns,zynq-gem # Xilinx Zynq-7xxx SoC 24 - cdns,zynqmp-gem # Xilinx Zynq Ultrascale+ MPSoC 25 - const: cdns,gem # Generic 26 27 - items: 28 - enum: 29 - cdns,at91sam9260-macb # Atmel at91sam9 SoCs 30 - cdns,sam9x60-macb # Microchip sam9x60 SoC 31 - const: cdns,macb # Generic 32 33 - items: 34 - enum: 35 - atmel,sama5d3-macb # 10/100Mbit IP on Atmel sama5d3 SoCs 36 - enum: 37 - cdns,at91sam9260-macb # Atmel at91sam9 SoCs. 38 - const: cdns,macb # Generic 39 40 - enum: 41 - atmel,sama5d29-gem # GEM XL IP (10/100) on Atmel sama5d29 SoCs 42 - atmel,sama5d2-gem # GEM IP (10/100) on Atmel sama5d2 SoCs 43 - atmel,sama5d3-gem # Gigabit IP on Atmel sama5d3 SoCs 44 - atmel,sama5d4-gem # GEM IP (10/100) on Atmel sama5d4 SoCs 45 - cdns,at32ap7000-macb # Other 10/100 usage or use the generic form 46 - cdns,np4-macb # NP4 SoC devices 47 - microchip,sama7g5-emac # Microchip SAMA7G5 ethernet interface 48 - microchip,sama7g5-gem # Microchip SAMA7G5 gigabit ethernet interface 49 - sifive,fu540-c000-gem # SiFive FU540-C000 SoC 50 - cdns,emac # Generic 51 - cdns,gem # Generic 52 - cdns,macb # Generic 53 54 reg: 55 minItems: 1 56 items: 57 - description: Basic register set 58 - description: GEMGXL Management block registers on SiFive FU540-C000 SoC 59 60 interrupts: 61 minItems: 1 62 maxItems: 8 63 description: One interrupt per available hardware queue 64 65 clocks: 66 minItems: 1 67 maxItems: 5 68 69 clock-names: 70 minItems: 1 71 items: 72 - enum: [ ether_clk, hclk, pclk ] 73 - enum: [ hclk, pclk ] 74 - const: tx_clk 75 - enum: [ rx_clk, tsu_clk ] 76 - const: tsu_clk 77 78 local-mac-address: true 79 80 phy-mode: true 81 82 phy-handle: true 83 84 phys: 85 maxItems: 1 86 87 phy-names: 88 const: sgmii-phy 89 description: 90 Required with ZynqMP SoC when in SGMII mode. 91 Should reference PS-GTR generic PHY device for this controller 92 instance. See ZynqMP example. 93 94 resets: 95 maxItems: 1 96 description: 97 Recommended with ZynqMP, specify reset control for this 98 controller instance with zynqmp-reset driver. 99 100 reset-names: 101 maxItems: 1 102 103 fixed-link: true 104 105 iommus: 106 maxItems: 1 107 108 power-domains: 109 maxItems: 1 110 111 '#address-cells': 112 const: 1 113 114 '#size-cells': 115 const: 0 116 117 mdio: 118 type: object 119 description: 120 Node containing PHY children. If this node is not present, then PHYs will 121 be direct children. 122 123patternProperties: 124 "^ethernet-phy@[0-9a-f]$": 125 type: object 126 $ref: ethernet-phy.yaml# 127 128 properties: 129 reset-gpios: true 130 131 magic-packet: 132 type: boolean 133 description: 134 Indicates that the hardware supports waking up via magic packet. 135 136 unevaluatedProperties: false 137 138required: 139 - compatible 140 - reg 141 - interrupts 142 - clocks 143 - clock-names 144 - phy-mode 145 146allOf: 147 - $ref: ethernet-controller.yaml# 148 149 - if: 150 not: 151 properties: 152 compatible: 153 contains: 154 const: sifive,fu540-c000-gem 155 then: 156 properties: 157 reg: 158 maxItems: 1 159 160unevaluatedProperties: false 161 162examples: 163 - | 164 macb0: ethernet@fffc4000 { 165 compatible = "cdns,at32ap7000-macb"; 166 reg = <0xfffc4000 0x4000>; 167 interrupts = <21>; 168 phy-mode = "rmii"; 169 local-mac-address = [3a 0e 03 04 05 06]; 170 clock-names = "pclk", "hclk", "tx_clk"; 171 clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>; 172 #address-cells = <1>; 173 #size-cells = <0>; 174 175 ethernet-phy@1 { 176 reg = <0x1>; 177 reset-gpios = <&pioE 6 1>; 178 }; 179 }; 180 181 - | 182 #include <dt-bindings/clock/xlnx-zynqmp-clk.h> 183 #include <dt-bindings/power/xlnx-zynqmp-power.h> 184 #include <dt-bindings/reset/xlnx-zynqmp-resets.h> 185 #include <dt-bindings/phy/phy.h> 186 187 bus { 188 #address-cells = <2>; 189 #size-cells = <2>; 190 gem1: ethernet@ff0c0000 { 191 compatible = "cdns,zynqmp-gem", "cdns,gem"; 192 interrupt-parent = <&gic>; 193 interrupts = <0 59 4>, <0 59 4>; 194 reg = <0x0 0xff0c0000 0x0 0x1000>; 195 clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>, 196 <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>, 197 <&zynqmp_clk GEM_TSU>; 198 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; 199 #address-cells = <1>; 200 #size-cells = <0>; 201 #stream-id-cells = <1>; 202 iommus = <&smmu 0x875>; 203 power-domains = <&zynqmp_firmware PD_ETH_1>; 204 resets = <&zynqmp_reset ZYNQMP_RESET_GEM1>; 205 reset-names = "gem1_rst"; 206 status = "okay"; 207 phy-mode = "sgmii"; 208 phy-names = "sgmii-phy"; 209 phys = <&psgtr 1 PHY_TYPE_SGMII 1 1>; 210 fixed-link { 211 speed = <1000>; 212 full-duplex; 213 pause; 214 }; 215 }; 216 }; 217