1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/can/st,stm32-bxcan.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: STMicroelectronics bxCAN controller
8
9description: STMicroelectronics BxCAN controller for CAN bus
10
11maintainers:
12  - Dario Binacchi <dario.binacchi@amarulasolutions.com>
13
14allOf:
15  - $ref: can-controller.yaml#
16
17properties:
18  compatible:
19    enum:
20      - st,stm32f4-bxcan
21
22  st,can-primary:
23    description:
24      Primary and secondary mode of the bxCAN peripheral is only relevant
25      if the chip has two CAN peripherals. In that case they share some
26      of the required logic.
27      To avoid misunderstandings, it should be noted that ST documentation
28      uses the terms master/slave instead of primary/secondary.
29    type: boolean
30
31  reg:
32    maxItems: 1
33
34  interrupts:
35    items:
36      - description: transmit interrupt
37      - description: FIFO 0 receive interrupt
38      - description: FIFO 1 receive interrupt
39      - description: status change error interrupt
40
41  interrupt-names:
42    items:
43      - const: tx
44      - const: rx0
45      - const: rx1
46      - const: sce
47
48  resets:
49    maxItems: 1
50
51  clocks:
52    maxItems: 1
53
54  st,gcan:
55    $ref: /schemas/types.yaml#/definitions/phandle-array
56    description:
57      The phandle to the gcan node which allows to access the 512-bytes
58      SRAM memory shared by the two bxCAN cells (CAN1 primary and CAN2
59      secondary) in dual CAN peripheral configuration.
60
61required:
62  - compatible
63  - reg
64  - interrupts
65  - resets
66  - clocks
67  - st,gcan
68
69additionalProperties: false
70
71examples:
72  - |
73    #include <dt-bindings/clock/stm32fx-clock.h>
74    #include <dt-bindings/mfd/stm32f4-rcc.h>
75
76    can1: can@40006400 {
77        compatible = "st,stm32f4-bxcan";
78        reg = <0x40006400 0x200>;
79        interrupts = <19>, <20>, <21>, <22>;
80        interrupt-names = "tx", "rx0", "rx1", "sce";
81        resets = <&rcc STM32F4_APB1_RESET(CAN1)>;
82        clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>;
83        st,can-primary;
84        st,gcan = <&gcan>;
85    };
86