1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/net/can/renesas,rcar-canfd.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Renesas R-Car CAN FD Controller 8 9maintainers: 10 - Fabrizio Castro <fabrizio.castro.jz@renesas.com> 11 12allOf: 13 - $ref: can-controller.yaml# 14 15properties: 16 compatible: 17 oneOf: 18 - items: 19 - enum: 20 - renesas,r8a774a1-canfd # RZ/G2M 21 - renesas,r8a774b1-canfd # RZ/G2N 22 - renesas,r8a774c0-canfd # RZ/G2E 23 - renesas,r8a774e1-canfd # RZ/G2H 24 - renesas,r8a7795-canfd # R-Car H3 25 - renesas,r8a7796-canfd # R-Car M3-W 26 - renesas,r8a77965-canfd # R-Car M3-N 27 - renesas,r8a77970-canfd # R-Car V3M 28 - renesas,r8a77980-canfd # R-Car V3H 29 - renesas,r8a77990-canfd # R-Car E3 30 - renesas,r8a77995-canfd # R-Car D3 31 - const: renesas,rcar-gen3-canfd # R-Car Gen3 and RZ/G2 32 33 - items: 34 - enum: 35 - renesas,r9a07g044-canfd # RZ/G2{L,LC} 36 - const: renesas,rzg2l-canfd # RZ/G2L family 37 38 - const: renesas,r8a779a0-canfd # R-Car V3U 39 40 reg: 41 maxItems: 1 42 43 interrupts: true 44 45 clocks: 46 maxItems: 3 47 48 clock-names: 49 items: 50 - const: fck 51 - const: canfd 52 - const: can_clk 53 54 power-domains: 55 maxItems: 1 56 57 resets: true 58 59 renesas,no-can-fd: 60 $ref: /schemas/types.yaml#/definitions/flag 61 description: 62 The controller can operate in either CAN FD only mode (default) or 63 Classical CAN only mode. The mode is global to both the channels. 64 Specify this property to put the controller in Classical CAN only mode. 65 66 assigned-clocks: 67 description: 68 Reference to the CANFD clock. The CANFD clock is a div6 clock and can be 69 used by both CAN (if present) and CAN FD controllers at the same time. 70 It needs to be scaled to maximum frequency if any of these controllers 71 use it. 72 73 assigned-clock-rates: 74 description: Maximum frequency of the CANFD clock. 75 76patternProperties: 77 "^channel[01]$": 78 type: object 79 description: 80 The controller supports two channels and each is represented as a child 81 node. Each child node supports the "status" property only, which 82 is used to enable/disable the respective channel. 83 84required: 85 - compatible 86 - reg 87 - interrupts 88 - clocks 89 - clock-names 90 - power-domains 91 - resets 92 - assigned-clocks 93 - assigned-clock-rates 94 - channel0 95 - channel1 96 97if: 98 properties: 99 compatible: 100 contains: 101 enum: 102 - renesas,rzg2l-canfd 103then: 104 properties: 105 interrupts: 106 items: 107 - description: CAN global error interrupt 108 - description: CAN receive FIFO interrupt 109 - description: CAN0 error interrupt 110 - description: CAN0 transmit interrupt 111 - description: CAN0 transmit/receive FIFO receive completion interrupt 112 - description: CAN1 error interrupt 113 - description: CAN1 transmit interrupt 114 - description: CAN1 transmit/receive FIFO receive completion interrupt 115 116 interrupt-names: 117 items: 118 - const: g_err 119 - const: g_recc 120 - const: ch0_err 121 - const: ch0_rec 122 - const: ch0_trx 123 - const: ch1_err 124 - const: ch1_rec 125 - const: ch1_trx 126 127 resets: 128 maxItems: 2 129 130 reset-names: 131 items: 132 - const: rstp_n 133 - const: rstc_n 134 135 required: 136 - interrupt-names 137 - reset-names 138else: 139 properties: 140 interrupts: 141 items: 142 - description: Channel interrupt 143 - description: Global interrupt 144 145 interrupt-names: 146 items: 147 - const: ch_int 148 - const: g_int 149 150 resets: 151 maxItems: 1 152 153unevaluatedProperties: false 154 155examples: 156 - | 157 #include <dt-bindings/clock/r8a7795-cpg-mssr.h> 158 #include <dt-bindings/interrupt-controller/arm-gic.h> 159 #include <dt-bindings/power/r8a7795-sysc.h> 160 161 canfd: can@e66c0000 { 162 compatible = "renesas,r8a7795-canfd", 163 "renesas,rcar-gen3-canfd"; 164 reg = <0xe66c0000 0x8000>; 165 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 166 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 167 clocks = <&cpg CPG_MOD 914>, 168 <&cpg CPG_CORE R8A7795_CLK_CANFD>, 169 <&can_clk>; 170 clock-names = "fck", "canfd", "can_clk"; 171 assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>; 172 assigned-clock-rates = <40000000>; 173 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 174 resets = <&cpg 914>; 175 176 channel0 { 177 }; 178 179 channel1 { 180 }; 181 }; 182