1d524dac9SGrant LikelyCAN Device Tree Bindings 2d524dac9SGrant Likely------------------------ 3d524dac9SGrant Likely 4d524dac9SGrant Likely(c) 2006-2009 Secret Lab Technologies Ltd 5d524dac9SGrant LikelyGrant Likely <grant.likely@secretlab.ca> 6d524dac9SGrant Likely 7d524dac9SGrant Likelyfsl,mpc5200-mscan nodes 8d524dac9SGrant Likely----------------------- 9d524dac9SGrant LikelyIn addition to the required compatible-, reg- and interrupt-properties, you can 10d524dac9SGrant Likelyalso specify which clock source shall be used for the controller: 11d524dac9SGrant Likely 12d524dac9SGrant Likely- fsl,mscan-clock-source : a string describing the clock source. Valid values 13d524dac9SGrant Likely are: "ip" for ip bus clock 14d524dac9SGrant Likely "ref" for reference clock (XTAL) 15d524dac9SGrant Likely "ref" is default in case this property is not 16d524dac9SGrant Likely present. 17d524dac9SGrant Likely 18d524dac9SGrant Likelyfsl,mpc5121-mscan nodes 19d524dac9SGrant Likely----------------------- 20d524dac9SGrant LikelyIn addition to the required compatible-, reg- and interrupt-properties, you can 21d524dac9SGrant Likelyalso specify which clock source and divider shall be used for the controller: 22d524dac9SGrant Likely 23d524dac9SGrant Likely- fsl,mscan-clock-source : a string describing the clock source. Valid values 24d524dac9SGrant Likely are: "ip" for ip bus clock 25d524dac9SGrant Likely "ref" for reference clock 26d524dac9SGrant Likely "sys" for system clock 27d524dac9SGrant Likely If this property is not present, an optimal CAN 28d524dac9SGrant Likely clock source and frequency based on the system 29d524dac9SGrant Likely clock will be selected. If this is not possible, 30d524dac9SGrant Likely the reference clock will be used. 31d524dac9SGrant Likely 32d524dac9SGrant Likely- fsl,mscan-clock-divider: for the reference and system clock, an additional 33d524dac9SGrant Likely clock divider can be specified. By default, a 34d524dac9SGrant Likely value of 1 is used. 35d524dac9SGrant Likely 36d524dac9SGrant LikelyNote that the MPC5121 Rev. 1 processor is not supported. 37d524dac9SGrant Likely 38d524dac9SGrant LikelyExamples: 39d524dac9SGrant Likely can@1300 { 40d524dac9SGrant Likely compatible = "fsl,mpc5121-mscan"; 41d524dac9SGrant Likely interrupts = <12 0x8>; 42d524dac9SGrant Likely interrupt-parent = <&ipic>; 43d524dac9SGrant Likely reg = <0x1300 0x80>; 44d524dac9SGrant Likely }; 45d524dac9SGrant Likely 46d524dac9SGrant Likely can@1380 { 47d524dac9SGrant Likely compatible = "fsl,mpc5121-mscan"; 48d524dac9SGrant Likely interrupts = <13 0x8>; 49d524dac9SGrant Likely interrupt-parent = <&ipic>; 50d524dac9SGrant Likely reg = <0x1380 0x80>; 51d524dac9SGrant Likely fsl,mscan-clock-source = "ref"; 52d524dac9SGrant Likely fsl,mscan-clock-divider = <3>; 53d524dac9SGrant Likely }; 54