1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/can/fsl,flexcan.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title:
8  Flexcan CAN controller on Freescale's ARM and PowerPC system-on-a-chip (SOC).
9
10maintainers:
11  - Marc Kleine-Budde <mkl@pengutronix.de>
12
13allOf:
14  - $ref: can-controller.yaml#
15
16properties:
17  compatible:
18    oneOf:
19      - enum:
20          - fsl,imx8qm-flexcan
21          - fsl,imx8mp-flexcan
22          - fsl,imx6q-flexcan
23          - fsl,imx28-flexcan
24          - fsl,imx25-flexcan
25          - fsl,p1010-flexcan
26          - fsl,vf610-flexcan
27          - fsl,ls1021ar2-flexcan
28          - fsl,lx2160ar1-flexcan
29      - items:
30          - enum:
31              - fsl,imx53-flexcan
32              - fsl,imx35-flexcan
33          - const: fsl,imx25-flexcan
34      - items:
35          - enum:
36              - fsl,imx7d-flexcan
37              - fsl,imx6ul-flexcan
38              - fsl,imx6sx-flexcan
39          - const: fsl,imx6q-flexcan
40      - items:
41          - enum:
42              - fsl,ls1028ar1-flexcan
43          - const: fsl,lx2160ar1-flexcan
44
45  reg:
46    maxItems: 1
47
48  interrupts:
49    maxItems: 1
50
51  clocks:
52    maxItems: 2
53
54  clock-names:
55    items:
56      - const: ipg
57      - const: per
58
59  clock-frequency:
60    $ref: /schemas/types.yaml#/definitions/uint32
61    description: |
62      The oscillator frequency driving the flexcan device, filled in by the
63      boot loader. This property should only be used the used operating system
64      doesn't support the clocks and clock-names property.
65
66  xceiver-supply:
67    description: Regulator that powers the CAN transceiver.
68
69  big-endian:
70    $ref: /schemas/types.yaml#/definitions/flag
71    description: |
72      This means the registers of FlexCAN controller are big endian. This is
73      optional property.i.e. if this property is not present in device tree
74      node then controller is assumed to be little endian. If this property is
75      present then controller is assumed to be big endian.
76
77  fsl,stop-mode:
78    description: |
79      Register bits of stop mode control.
80
81      The format should be as follows:
82      <gpr req_gpr req_bit>
83      gpr is the phandle to general purpose register node.
84      req_gpr is the gpr register offset of CAN stop request.
85      req_bit is the bit offset of CAN stop request.
86    $ref: /schemas/types.yaml#/definitions/phandle-array
87    items:
88      items:
89        - description: The 'gpr' is the phandle to general purpose register node.
90        - description: The 'req_gpr' is the gpr register offset of CAN stop request.
91          maximum: 0xff
92        - description: The 'req_bit' is the bit offset of CAN stop request.
93          maximum: 0x1f
94
95  fsl,clk-source:
96    description: |
97      Select the clock source to the CAN Protocol Engine (PE). It's SoC
98      implementation dependent. Refer to RM for detailed definition. If this
99      property is not set in device tree node then driver selects clock source 1
100      by default.
101      0: clock source 0 (oscillator clock)
102      1: clock source 1 (peripheral clock)
103    $ref: /schemas/types.yaml#/definitions/uint8
104    default: 1
105    minimum: 0
106    maximum: 1
107
108  wakeup-source:
109    $ref: /schemas/types.yaml#/definitions/flag
110    description:
111      Enable CAN remote wakeup.
112
113  fsl,scu-index:
114    description: |
115      The scu index of CAN instance.
116      For SoCs with SCU support, need setup stop mode via SCU firmware, so this
117      property can help indicate a resource. It supports up to 3 CAN instances
118      now.
119    $ref: /schemas/types.yaml#/definitions/uint8
120    minimum: 0
121    maximum: 2
122
123required:
124  - compatible
125  - reg
126  - interrupts
127
128additionalProperties: false
129
130examples:
131  - |
132    can@1c000 {
133        compatible = "fsl,p1010-flexcan";
134        reg = <0x1c000 0x1000>;
135        interrupts = <48 0x2>;
136        interrupt-parent = <&mpic>;
137        clock-frequency = <200000000>;
138        fsl,clk-source = /bits/ 8 <0>;
139    };
140  - |
141    #include <dt-bindings/interrupt-controller/irq.h>
142
143    can@2090000 {
144        compatible = "fsl,imx6q-flexcan";
145        reg = <0x02090000 0x4000>;
146        interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
147        clocks = <&clks 1>, <&clks 2>;
148        clock-names = "ipg", "per";
149        fsl,stop-mode = <&gpr 0x34 28>;
150        fsl,scu-index = /bits/ 8 <1>;
151    };
152