1*1da9d6e3SPavel Pisa# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*1da9d6e3SPavel Pisa%YAML 1.2 3*1da9d6e3SPavel Pisa--- 4*1da9d6e3SPavel Pisa$id: http://devicetree.org/schemas/net/can/ctu,ctucanfd.yaml# 5*1da9d6e3SPavel Pisa$schema: http://devicetree.org/meta-schemas/core.yaml# 6*1da9d6e3SPavel Pisa 7*1da9d6e3SPavel Pisatitle: CTU CAN FD Open-source IP Core Device Tree Bindings 8*1da9d6e3SPavel Pisa 9*1da9d6e3SPavel Pisadescription: | 10*1da9d6e3SPavel Pisa Open-source CAN FD IP core developed at the Czech Technical University in Prague 11*1da9d6e3SPavel Pisa 12*1da9d6e3SPavel Pisa The core sources and documentation on project page 13*1da9d6e3SPavel Pisa [1] sources : https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core 14*1da9d6e3SPavel Pisa [2] datasheet : https://canbus.pages.fel.cvut.cz/ctucanfd_ip_core/doc/Datasheet.pdf 15*1da9d6e3SPavel Pisa 16*1da9d6e3SPavel Pisa Integration in Xilinx Zynq SoC based system together with 17*1da9d6e3SPavel Pisa OpenCores SJA1000 compatible controllers 18*1da9d6e3SPavel Pisa [3] project : https://gitlab.fel.cvut.cz/canbus/zynq/zynq-can-sja1000-top 19*1da9d6e3SPavel Pisa Martin Jerabek dimploma thesis with integration and testing 20*1da9d6e3SPavel Pisa framework description 21*1da9d6e3SPavel Pisa [4] PDF : https://dspace.cvut.cz/bitstream/handle/10467/80366/F3-DP-2019-Jerabek-Martin-Jerabek-thesis-2019-canfd.pdf 22*1da9d6e3SPavel Pisa 23*1da9d6e3SPavel Pisamaintainers: 24*1da9d6e3SPavel Pisa - Pavel Pisa <pisa@cmp.felk.cvut.cz> 25*1da9d6e3SPavel Pisa - Ondrej Ille <ondrej.ille@gmail.com> 26*1da9d6e3SPavel Pisa - Martin Jerabek <martin.jerabek01@gmail.com> 27*1da9d6e3SPavel Pisa 28*1da9d6e3SPavel Pisaproperties: 29*1da9d6e3SPavel Pisa compatible: 30*1da9d6e3SPavel Pisa oneOf: 31*1da9d6e3SPavel Pisa - items: 32*1da9d6e3SPavel Pisa - const: ctu,ctucanfd-2 33*1da9d6e3SPavel Pisa - const: ctu,ctucanfd 34*1da9d6e3SPavel Pisa - const: ctu,ctucanfd 35*1da9d6e3SPavel Pisa 36*1da9d6e3SPavel Pisa reg: 37*1da9d6e3SPavel Pisa maxItems: 1 38*1da9d6e3SPavel Pisa 39*1da9d6e3SPavel Pisa interrupts: 40*1da9d6e3SPavel Pisa maxItems: 1 41*1da9d6e3SPavel Pisa 42*1da9d6e3SPavel Pisa clocks: 43*1da9d6e3SPavel Pisa description: | 44*1da9d6e3SPavel Pisa phandle of reference clock (100 MHz is appropriate 45*1da9d6e3SPavel Pisa for FPGA implementation on Zynq-7000 system). 46*1da9d6e3SPavel Pisa maxItems: 1 47*1da9d6e3SPavel Pisa 48*1da9d6e3SPavel Pisarequired: 49*1da9d6e3SPavel Pisa - compatible 50*1da9d6e3SPavel Pisa - reg 51*1da9d6e3SPavel Pisa - interrupts 52*1da9d6e3SPavel Pisa - clocks 53*1da9d6e3SPavel Pisa 54*1da9d6e3SPavel PisaadditionalProperties: false 55*1da9d6e3SPavel Pisa 56*1da9d6e3SPavel Pisaexamples: 57*1da9d6e3SPavel Pisa - | 58*1da9d6e3SPavel Pisa ctu_can_fd_0: can@43c30000 { 59*1da9d6e3SPavel Pisa compatible = "ctu,ctucanfd"; 60*1da9d6e3SPavel Pisa interrupts = <0 30 4>; 61*1da9d6e3SPavel Pisa clocks = <&clkc 15>; 62*1da9d6e3SPavel Pisa reg = <0x43c30000 0x10000>; 63*1da9d6e3SPavel Pisa }; 64