1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/brcm,unimac-mdio.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Broadcom UniMAC MDIO bus controller
8
9maintainers:
10  - Doug Berger <opendmb@gmail.com>
11  - Florian Fainelli <f.fainelli@gmail.com>
12  - Rafał Miłecki <rafal@milecki.pl>
13
14allOf:
15  - $ref: mdio.yaml#
16
17properties:
18  compatible:
19    enum:
20      - brcm,genet-mdio-v1
21      - brcm,genet-mdio-v2
22      - brcm,genet-mdio-v3
23      - brcm,genet-mdio-v4
24      - brcm,genet-mdio-v5
25      - brcm,unimac-mdio
26
27  reg:
28    minItems: 1
29    items:
30      - description: base register
31      - description: indirect accesses to larger than 16-bits MDIO transactions
32
33  reg-names:
34    minItems: 1
35    items:
36      - const: mdio
37      - const: mdio_indir_rw
38
39  interrupts:
40    oneOf:
41      - description: >
42          Interrupt shared with the Ethernet MAC or Ethernet switch this MDIO
43          block is integrated from
44      - items:
45          - description: |
46              "mdio done" interrupt
47          - description: |
48              "mdio error" interrupt
49
50  interrupt-names:
51    oneOf:
52      - const: mdio_done_error
53      - items:
54          - const: mdio_done
55          - const: mdio_error
56
57  clocks:
58    description: A reference to the clock supplying the MDIO bus controller
59
60  clock-frequency:
61    description: >
62      The MDIO bus clock that must be output by the MDIO bus hardware, if
63      absent, the default hardware values are used
64
65unevaluatedProperties: false
66
67required:
68  - reg
69  - '#address-cells'
70  - '#size-cells'
71
72examples:
73  - |
74    mdio@403c0 {
75        compatible = "brcm,unimac-mdio";
76        reg = <0x403c0 0x8>, <0x40300 0x18>;
77        reg-names = "mdio", "mdio_indir_rw";
78        #address-cells = <1>;
79        #size-cells = <0>;
80
81        ethernet-phy@0 {
82            compatible = "ethernet-phy-ieee802.3-c22";
83            reg = <0>;
84        };
85    };
86