1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2# Copyright 2019 BayLibre, SAS
3%YAML 1.2
4---
5$id: "http://devicetree.org/schemas/net/amlogic,meson-dwmac.yaml#"
6$schema: "http://devicetree.org/meta-schemas/core.yaml#"
7
8title: Amlogic Meson DWMAC Ethernet controller
9
10maintainers:
11  - Neil Armstrong <narmstrong@baylibre.com>
12  - Martin Blumenstingl <martin.blumenstingl@googlemail.com>
13
14# We need a select here so we don't match all nodes with 'snps,dwmac'
15select:
16  properties:
17    compatible:
18      contains:
19        enum:
20          - amlogic,meson6-dwmac
21          - amlogic,meson8b-dwmac
22          - amlogic,meson8m2-dwmac
23          - amlogic,meson-gxbb-dwmac
24          - amlogic,meson-axg-dwmac
25  required:
26    - compatible
27
28allOf:
29  - $ref: "snps,dwmac.yaml#"
30  - if:
31      properties:
32        compatible:
33          contains:
34            enum:
35              - amlogic,meson8b-dwmac
36              - amlogic,meson8m2-dwmac
37              - amlogic,meson-gxbb-dwmac
38              - amlogic,meson-axg-dwmac
39
40    then:
41      properties:
42        clocks:
43          minItems: 3
44          maxItems: 4
45          items:
46            - description: GMAC main clock
47            - description: First parent clock of the internal mux
48            - description: Second parent clock of the internal mux
49            - description: The clock which drives the timing adjustment logic
50
51        clock-names:
52          minItems: 3
53          maxItems: 4
54          items:
55            - const: stmmaceth
56            - const: clkin0
57            - const: clkin1
58            - const: timing-adjustment
59
60        amlogic,tx-delay-ns:
61          $ref: /schemas/types.yaml#definitions/uint32
62          description:
63            The internal RGMII TX clock delay (provided by this driver) in
64            nanoseconds. Allowed values are 0ns, 2ns, 4ns, 6ns.
65            When phy-mode is set to "rgmii" then the TX delay should be
66            explicitly configured. When not configured a fallback of 2ns is
67            used. When the phy-mode is set to either "rgmii-id" or "rgmii-txid"
68            the TX clock delay is already provided by the PHY. In that case
69            this property should be set to 0ns (which disables the TX clock
70            delay in the MAC to prevent the clock from going off because both
71            PHY and MAC are adding a delay).
72            Any configuration is ignored when the phy-mode is set to "rmii".
73
74        amlogic,rx-delay-ns:
75          enum:
76            - 0
77            - 2
78          default: 0
79          description:
80            The internal RGMII RX clock delay (provided by this IP block) in
81            nanoseconds. When phy-mode is set to "rgmii" then the RX delay
82            should be explicitly configured. When the phy-mode is set to
83            either "rgmii-id" or "rgmii-rxid" the RX clock delay is already
84            provided by the PHY. Any configuration is ignored when the
85            phy-mode is set to "rmii".
86
87properties:
88  compatible:
89    additionalItems: true
90    maxItems: 3
91    items:
92      - enum:
93          - amlogic,meson6-dwmac
94          - amlogic,meson8b-dwmac
95          - amlogic,meson8m2-dwmac
96          - amlogic,meson-gxbb-dwmac
97          - amlogic,meson-axg-dwmac
98    contains:
99      enum:
100        - snps,dwmac-3.70a
101        - snps,dwmac
102
103  reg:
104    items:
105      - description:
106          The first register range should be the one of the DWMAC controller
107      - description:
108          The second range is is for the Amlogic specific configuration
109          (for example the PRG_ETHERNET register range on Meson8b and newer)
110
111required:
112  - compatible
113  - reg
114  - interrupts
115  - interrupt-names
116  - clocks
117  - clock-names
118  - phy-mode
119
120examples:
121  - |
122    ethmac: ethernet@c9410000 {
123         compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac";
124         reg = <0xc9410000 0x10000>, <0xc8834540 0x8>;
125         interrupts = <8>;
126         interrupt-names = "macirq";
127         clocks = <&clk_eth>, <&clk_fclk_div2>, <&clk_mpll2>, <&clk_fclk_div2>;
128         clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment";
129         phy-mode = "rgmii";
130    };
131