1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/allwinner,sun8i-a83t-emac.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Allwinner A83t EMAC Device Tree Bindings
8
9maintainers:
10  - Chen-Yu Tsai <wens@csie.org>
11  - Maxime Ripard <mripard@kernel.org>
12
13properties:
14  compatible:
15    oneOf:
16      - const: allwinner,sun8i-a83t-emac
17      - const: allwinner,sun8i-h3-emac
18      - const: allwinner,sun8i-r40-emac
19      - const: allwinner,sun8i-v3s-emac
20      - const: allwinner,sun50i-a64-emac
21      - items:
22          - enum:
23              - allwinner,sun20i-d1-emac
24              - allwinner,sun50i-h6-emac
25          - const: allwinner,sun50i-a64-emac
26
27  reg:
28    maxItems: 1
29
30  interrupts:
31    maxItems: 1
32
33  interrupt-names:
34    const: macirq
35
36  clocks:
37    maxItems: 1
38
39  clock-names:
40    const: stmmaceth
41
42  syscon:
43    $ref: /schemas/types.yaml#/definitions/phandle
44    description:
45      Phandle to the device containing the EMAC or GMAC clock
46      register
47
48required:
49  - compatible
50  - reg
51  - interrupts
52  - interrupt-names
53  - clocks
54  - clock-names
55  - resets
56  - reset-names
57  - phy-handle
58  - phy-mode
59  - syscon
60
61allOf:
62  - $ref: "snps,dwmac.yaml#"
63  - if:
64      properties:
65        compatible:
66          contains:
67            enum:
68              - allwinner,sun8i-a83t-emac
69              - allwinner,sun8i-h3-emac
70              - allwinner,sun8i-v3s-emac
71              - allwinner,sun50i-a64-emac
72
73    then:
74      properties:
75        allwinner,tx-delay-ps:
76          default: 0
77          minimum: 0
78          maximum: 700
79          multipleOf: 100
80          description:
81            External RGMII PHY TX clock delay chain value in ps.
82
83        allwinner,rx-delay-ps:
84          default: 0
85          minimum: 0
86          maximum: 3100
87          multipleOf: 100
88          description:
89            External RGMII PHY TX clock delay chain value in ps.
90
91  - if:
92      properties:
93        compatible:
94          contains:
95            enum:
96              - allwinner,sun8i-r40-emac
97
98    then:
99      properties:
100        allwinner,rx-delay-ps:
101          default: 0
102          minimum: 0
103          maximum: 700
104          multipleOf: 100
105          description:
106            External RGMII PHY TX clock delay chain value in ps.
107
108  - if:
109      properties:
110        compatible:
111          contains:
112            enum:
113              - allwinner,sun8i-h3-emac
114              - allwinner,sun8i-v3s-emac
115
116    then:
117      properties:
118        allwinner,leds-active-low:
119          $ref: /schemas/types.yaml#/definitions/flag
120          description:
121            EPHY LEDs are active low.
122
123        mdio-mux:
124          type: object
125
126          properties:
127            compatible:
128              const: allwinner,sun8i-h3-mdio-mux
129
130            mdio-parent-bus:
131              $ref: /schemas/types.yaml#/definitions/phandle
132              description:
133                Phandle to EMAC MDIO.
134
135            mdio@1:
136              type: object
137              description: Internal MDIO Bus
138
139              properties:
140                "#address-cells":
141                  const: 1
142
143                "#size-cells":
144                  const: 0
145
146                compatible:
147                  const: allwinner,sun8i-h3-mdio-internal
148
149                reg:
150                  const: 1
151
152              patternProperties:
153                "^ethernet-phy@[0-9a-f]$":
154                  type: object
155                  description:
156                    Integrated PHY node
157
158                  properties:
159                    clocks:
160                      maxItems: 1
161
162                    resets:
163                      maxItems: 1
164
165                  required:
166                    - clocks
167                    - resets
168
169
170            mdio@2:
171              type: object
172              description: External MDIO Bus (H3 only)
173
174              properties:
175                "#address-cells":
176                  const: 1
177
178                "#size-cells":
179                  const: 0
180
181                reg:
182                  const: 2
183
184          required:
185            - compatible
186            - mdio-parent-bus
187            - mdio@1
188
189unevaluatedProperties: false
190
191examples:
192  - |
193    ethernet@1c0b000 {
194        compatible = "allwinner,sun8i-h3-emac";
195        syscon = <&syscon>;
196        reg = <0x01c0b000 0x104>;
197        interrupts = <0 82 1>;
198        interrupt-names = "macirq";
199        resets = <&ccu 12>;
200        reset-names = "stmmaceth";
201        clocks = <&ccu 27>;
202        clock-names = "stmmaceth";
203
204        phy-handle = <&int_mii_phy>;
205        phy-mode = "mii";
206        allwinner,leds-active-low;
207
208        mdio1: mdio {
209            #address-cells = <1>;
210            #size-cells = <0>;
211            compatible = "snps,dwmac-mdio";
212        };
213
214        mdio-mux {
215            compatible = "allwinner,sun8i-h3-mdio-mux";
216            #address-cells = <1>;
217            #size-cells = <0>;
218
219            mdio-parent-bus = <&mdio1>;
220
221            int_mii_phy: mdio@1 {
222                compatible = "allwinner,sun8i-h3-mdio-internal";
223                reg = <1>;
224                #address-cells = <1>;
225                #size-cells = <0>;
226
227                ethernet-phy@1 {
228                    reg = <1>;
229                    clocks = <&ccu 67>;
230                    resets = <&ccu 39>;
231                    phy-is-integrated;
232                };
233            };
234
235            mdio@2 {
236                reg = <2>;
237                #address-cells = <1>;
238                #size-cells = <0>;
239            };
240        };
241    };
242
243  - |
244    ethernet@1c0b000 {
245        compatible = "allwinner,sun8i-h3-emac";
246        syscon = <&syscon>;
247        reg = <0x01c0b000 0x104>;
248        interrupts = <0 82 1>;
249        interrupt-names = "macirq";
250        resets = <&ccu 12>;
251        reset-names = "stmmaceth";
252        clocks = <&ccu 27>;
253        clock-names = "stmmaceth";
254
255        phy-handle = <&ext_rgmii_phy>;
256        phy-mode = "rgmii";
257        allwinner,leds-active-low;
258
259        mdio2: mdio {
260            #address-cells = <1>;
261            #size-cells = <0>;
262            compatible = "snps,dwmac-mdio";
263        };
264
265        mdio-mux {
266            compatible = "allwinner,sun8i-h3-mdio-mux";
267            #address-cells = <1>;
268            #size-cells = <0>;
269            mdio-parent-bus = <&mdio2>;
270
271            mdio@1 {
272                compatible = "allwinner,sun8i-h3-mdio-internal";
273                reg = <1>;
274                #address-cells = <1>;
275                #size-cells = <0>;
276
277                ethernet-phy@1 {
278                    reg = <1>;
279                    clocks = <&ccu 67>;
280                    resets = <&ccu 39>;
281                };
282            };
283
284            mdio@2 {
285                reg = <2>;
286                #address-cells = <1>;
287                #size-cells = <0>;
288
289                ext_rgmii_phy: ethernet-phy@1 {
290                    reg = <1>;
291                };
292            };
293        };
294    };
295
296  - |
297    ethernet@1c0b000 {
298        compatible = "allwinner,sun8i-a83t-emac";
299        syscon = <&syscon>;
300        reg = <0x01c0b000 0x104>;
301        interrupts = <0 82 1>;
302        interrupt-names = "macirq";
303        resets = <&ccu 13>;
304        reset-names = "stmmaceth";
305        clocks = <&ccu 27>;
306        clock-names = "stmmaceth";
307        phy-handle = <&ext_rgmii_phy1>;
308        phy-mode = "rgmii";
309
310        mdio {
311            compatible = "snps,dwmac-mdio";
312            #address-cells = <1>;
313            #size-cells = <0>;
314
315            ext_rgmii_phy1: ethernet-phy@1 {
316                reg = <1>;
317            };
318        };
319    };
320
321...
322