1# SPDX-License-Identifier: GPL-2.0+
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/adi,adin.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Analog Devices ADIN1200/ADIN1300 PHY
8
9maintainers:
10  - Alexandru Ardelean <alexandru.ardelean@analog.com>
11
12description: |
13  Bindings for Analog Devices Industrial Ethernet PHYs
14
15allOf:
16  - $ref: ethernet-phy.yaml#
17
18properties:
19  adi,rx-internal-delay-ps:
20    description: |
21      RGMII RX Clock Delay used only when PHY operates in RGMII mode with
22      internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
23    enum: [ 1600, 1800, 2000, 2200, 2400 ]
24    default: 2000
25
26  adi,tx-internal-delay-ps:
27    description: |
28      RGMII TX Clock Delay used only when PHY operates in RGMII mode with
29      internal delay (phy-mode is 'rgmii-id' or 'rgmii-txid') in pico-seconds.
30    enum: [ 1600, 1800, 2000, 2200, 2400 ]
31    default: 2000
32
33  adi,fifo-depth-bits:
34    description: |
35      When operating in RMII mode, this option configures the FIFO depth.
36    enum: [ 4, 8, 12, 16, 20, 24 ]
37    default: 8
38
39  adi,disable-energy-detect:
40    description: |
41      Disables Energy Detect Powerdown Mode (default disabled, i.e energy detect
42      is enabled if this property is unspecified)
43    type: boolean
44
45examples:
46  - |
47    ethernet {
48        #address-cells = <1>;
49        #size-cells = <0>;
50
51        phy-mode = "rgmii-id";
52
53        ethernet-phy@0 {
54            reg = <0>;
55
56            adi,rx-internal-delay-ps = <1800>;
57            adi,tx-internal-delay-ps = <2200>;
58        };
59    };
60  - |
61    ethernet {
62        #address-cells = <1>;
63        #size-cells = <0>;
64
65        phy-mode = "rmii";
66
67        ethernet-phy@1 {
68            reg = <1>;
69
70            adi,fifo-depth-bits = <16>;
71            adi,disable-energy-detect;
72        };
73    };
74