xref: /openbmc/linux/Documentation/devicetree/bindings/net/adi,adin.yaml (revision df202b452fe6c6d6f1351bad485e2367ef1e644e) 
1# SPDX-License-Identifier: GPL-2.0+
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/adi,adin.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Analog Devices ADIN1200/ADIN1300 PHY
8
9maintainers:
10  - Alexandru Ardelean <alexandru.ardelean@analog.com>
11
12description: |
13  Bindings for Analog Devices Industrial Ethernet PHYs
14
15allOf:
16  - $ref: ethernet-phy.yaml#
17
18properties:
19  adi,rx-internal-delay-ps:
20    description: |
21      RGMII RX Clock Delay used only when PHY operates in RGMII mode with
22      internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
23    enum: [ 1600, 1800, 2000, 2200, 2400 ]
24    default: 2000
25
26  adi,tx-internal-delay-ps:
27    description: |
28      RGMII TX Clock Delay used only when PHY operates in RGMII mode with
29      internal delay (phy-mode is 'rgmii-id' or 'rgmii-txid') in pico-seconds.
30    enum: [ 1600, 1800, 2000, 2200, 2400 ]
31    default: 2000
32
33  adi,fifo-depth-bits:
34    description: |
35      When operating in RMII mode, this option configures the FIFO depth.
36    enum: [ 4, 8, 12, 16, 20, 24 ]
37    default: 8
38
39  adi,phy-output-clock:
40    description: Select clock output on GP_CLK pin. Two clocks are available:
41      A 25MHz reference and a free-running 125MHz.
42      The phy can alternatively automatically switch between the reference and
43      the 125MHz clocks based on its internal state.
44    $ref: /schemas/types.yaml#/definitions/string
45    enum:
46      - 25mhz-reference
47      - 125mhz-free-running
48      - adaptive-free-running
49
50  adi,phy-output-reference-clock:
51    description: Enable 25MHz reference clock output on CLK25_REF pin.
52    type: boolean
53
54unevaluatedProperties: false
55
56examples:
57  - |
58    ethernet {
59        #address-cells = <1>;
60        #size-cells = <0>;
61
62        phy-mode = "rgmii-id";
63
64        ethernet-phy@0 {
65            reg = <0>;
66
67            adi,rx-internal-delay-ps = <1800>;
68            adi,tx-internal-delay-ps = <2200>;
69        };
70    };
71  - |
72    ethernet {
73        #address-cells = <1>;
74        #size-cells = <0>;
75
76        phy-mode = "rmii";
77
78        ethernet-phy@1 {
79            reg = <1>;
80
81            adi,fifo-depth-bits = <16>;
82        };
83    };
84