1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mux/reg-mux.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Generic register bitfield-based multiplexer controller bindings
8
9maintainers:
10  - Peter Rosin <peda@axentia.se>
11
12description: |+
13  Define register bitfields to be used to control multiplexers. The parent
14  device tree node must be a device node to provide register r/w access.
15
16properties:
17  compatible:
18    enum:
19      - reg-mux   # parent device of mux controller is not syscon device
20      - mmio-mux  # parent device of mux controller is syscon device
21
22  reg: true
23
24  '#mux-control-cells':
25    const: 1
26
27  mux-reg-masks:
28    $ref: /schemas/types.yaml#/definitions/uint32-matrix
29    items:
30      items:
31        - description: register offset
32        - description: pre-shifted bitfield mask
33    description: Each entry pair describes a single mux control.
34
35  idle-states: true
36
37required:
38  - compatible
39  - mux-reg-masks
40  - '#mux-control-cells'
41
42additionalProperties: false
43
44examples:
45  - |
46    /* The parent device of mux controller is not a syscon device. */
47
48    #include <dt-bindings/mux/mux.h>
49
50    mux-controller {
51        compatible = "reg-mux";
52        #mux-control-cells = <1>;
53        mux-reg-masks =
54            <0x54 0xf8>, /* 0: reg 0x54, bits 7:3 */
55            <0x54 0x07>; /* 1: reg 0x54, bits 2:0 */
56    };
57
58    mdio-mux-1 {
59        compatible = "mdio-mux-multiplexer";
60        mux-controls = <&mux1 0>;
61        mdio-parent-bus = <&emdio1>;
62        #address-cells = <1>;
63        #size-cells = <0>;
64
65        mdio@0 {
66            reg = <0x0>;
67            #address-cells = <1>;
68            #size-cells = <0>;
69        };
70
71        mdio@8 {
72            reg = <0x8>;
73            #address-cells = <1>;
74            #size-cells = <0>;
75        };
76    };
77
78    mdio-mux-2 {
79        compatible = "mdio-mux-multiplexer";
80        mux-controls = <&mux1 1>;
81        mdio-parent-bus = <&emdio2>;
82        #address-cells = <1>;
83        #size-cells = <0>;
84
85        mdio@0 {
86            reg = <0x0>;
87            #address-cells = <1>;
88            #size-cells = <0>;
89        };
90
91        mdio@1 {
92            reg = <0x1>;
93            #address-cells = <1>;
94            #size-cells = <0>;
95        };
96    };
97
98  - |
99    /* The parent device of mux controller is syscon device. */
100
101    #include <dt-bindings/mux/mux.h>
102    syscon@1000 {
103        compatible = "fsl,imx7d-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", "syscon", "simple-mfd";
104        reg = <0x1000 0x100>;
105
106        mux2: mux-controller {
107            compatible = "mmio-mux";
108            #mux-control-cells = <1>;
109
110            mux-reg-masks =
111                <0x3 0x30>, /* 0: reg 0x3, bits 5:4 */
112                <0x3 0x40>; /* 1: reg 0x3, bit 6 */
113            idle-states = <MUX_IDLE_AS_IS>, <0>;
114        };
115    };
116
117    video-mux {
118        compatible = "video-mux";
119        mux-controls = <&mux2 0>;
120        #address-cells = <1>;
121        #size-cells = <0>;
122
123        ports {
124            #address-cells = <1>;
125            #size-cells = <0>;
126
127            /* inputs 0..3 */
128            port@0 {
129                reg = <0>;
130            };
131            port@1 {
132                reg = <1>;
133            };
134            port@2 {
135                reg = <2>;
136            };
137            port@3 {
138                reg = <3>;
139            };
140
141            /* output */
142            port@4 {
143                reg = <4>;
144            };
145        };
146    };
147...
148