1Freescale's NAND flash controller (NFC) 2 3This variant of the Freescale NAND flash controller (NFC) can be found on 4Vybrid (vf610), MPC5125, MCF54418 and Kinetis K70. 5 6Required properties: 7- compatible: Should be set to "fsl,vf610-nfc". 8- reg: address range of the NFC. 9- interrupts: interrupt of the NFC. 10- #address-cells: shall be set to 1. Encode the nand CS. 11- #size-cells : shall be set to 0. 12- assigned-clocks: main clock from the SoC, for Vybrid <&clks VF610_CLK_NFC>; 13- assigned-clock-rates: The NAND bus timing is derived from this clock 14 rate and should not exceed maximum timing for any NAND memory chip 15 in a board stuffing. Typical NAND memory timings derived from this 16 clock are found in the SoC hardware reference manual. Furthermore, 17 there might be restrictions on maximum rates when using hardware ECC. 18 19- #address-cells, #size-cells : Must be present if the device has sub-nodes 20 representing partitions. 21 22Required children nodes: 23Children nodes represent the available nand chips. Currently the driver can 24only handle one NAND chip. 25 26Required properties: 27- compatible: Should be set to "fsl,vf610-nfc-cs". 28- nand-bus-width: see nand.txt 29- nand-ecc-mode: see nand.txt 30 31Required properties for hardware ECC: 32- nand-ecc-strength: supported strengths are 24 and 32 bit (see nand.txt) 33- nand-ecc-step-size: step size equals page size, currently only 2k pages are 34 supported 35- nand-on-flash-bbt: see nand.txt 36 37Example: 38 39 nfc: nand@400e0000 { 40 compatible = "fsl,vf610-nfc"; 41 #address-cells = <1>; 42 #size-cells = <0>; 43 reg = <0x400e0000 0x4000>; 44 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 45 clocks = <&clks VF610_CLK_NFC>; 46 clock-names = "nfc"; 47 assigned-clocks = <&clks VF610_CLK_NFC>; 48 assigned-clock-rates = <33000000>; 49 50 nand@0 { 51 compatible = "fsl,vf610-nfc-nandcs"; 52 reg = <0>; 53 nand-bus-width = <8>; 54 nand-ecc-mode = "hw"; 55 nand-ecc-strength = <32>; 56 nand-ecc-step-size = <2048>; 57 nand-on-flash-bbt; 58 }; 59 }; 60