1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mtd/qcom,nandc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm NAND controller
8
9maintainers:
10  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
11
12properties:
13  compatible:
14    enum:
15      - qcom,ipq806x-nand
16      - qcom,ipq4019-nand
17      - qcom,ipq6018-nand
18      - qcom,ipq8074-nand
19      - qcom,sdx55-nand
20
21  reg:
22    maxItems: 1
23
24  clocks:
25    items:
26      - description: Core Clock
27      - description: Always ON Clock
28
29  clock-names:
30    items:
31      - const: core
32      - const: aon
33
34patternProperties:
35  "^nand@[a-f0-9]$":
36    type: object
37    $ref: raw-nand-chip.yaml
38    properties:
39
40      nand-bus-width:
41        const: 8
42
43      nand-ecc-strength:
44        enum: [1, 4, 8]
45
46      nand-ecc-step-size:
47        enum:
48          - 512
49
50      qcom,boot-partitions:
51        $ref: /schemas/types.yaml#/definitions/uint32-matrix
52        items:
53          items:
54            - description: offset
55            - description: size
56        description:
57          Boot partition use a different layout where the 4 bytes of spare
58          data are not protected by ECC. Use this to declare these special
59          partitions by defining first the offset and then the size.
60
61          It's in the form of <offset1 size1 offset2 size2 offset3 ...>
62          and should be declared in ascending order.
63
64          Refer to the ipq8064 example on how to use this special binding.
65
66    unevaluatedProperties: false
67
68allOf:
69  - $ref: nand-controller.yaml#
70
71  - if:
72      properties:
73        compatible:
74          contains:
75            const: qcom,ipq806x-nand
76    then:
77      properties:
78        dmas:
79          items:
80            - description: rxtx DMA channel
81
82        dma-names:
83          items:
84            - const: rxtx
85
86        qcom,cmd-crci:
87          $ref: /schemas/types.yaml#/definitions/uint32
88          description:
89            Must contain the ADM command type CRCI block instance number
90            specified for the NAND controller on the given platform
91
92        qcom,data-crci:
93          $ref: /schemas/types.yaml#/definitions/uint32
94          description:
95            Must contain the ADM data type CRCI block instance number
96            specified for the NAND controller on the given platform
97
98  - if:
99      properties:
100        compatible:
101          contains:
102            enum:
103              - qcom,ipq4019-nand
104              - qcom,ipq6018-nand
105              - qcom,ipq8074-nand
106              - qcom,sdx55-nand
107
108    then:
109      properties:
110        dmas:
111          items:
112            - description: tx DMA channel
113            - description: rx DMA channel
114            - description: cmd DMA channel
115
116        dma-names:
117          items:
118            - const: tx
119            - const: rx
120            - const: cmd
121
122  - if:
123      properties:
124        compatible:
125          contains:
126            enum:
127              - qcom,ipq806x-nand
128
129    then:
130      patternProperties:
131        "^nand@[a-f0-9]$":
132          properties:
133            qcom,boot-partitions: true
134    else:
135      patternProperties:
136        "^nand@[a-f0-9]$":
137          properties:
138            qcom,boot-partitions: false
139
140required:
141  - compatible
142  - reg
143  - clocks
144  - clock-names
145
146unevaluatedProperties: false
147
148examples:
149  - |
150    #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
151    nand-controller@1ac00000 {
152        compatible = "qcom,ipq806x-nand";
153        reg = <0x1ac00000 0x800>;
154
155        clocks = <&gcc EBI2_CLK>,
156                 <&gcc EBI2_AON_CLK>;
157        clock-names = "core", "aon";
158
159        dmas = <&adm_dma 3>;
160        dma-names = "rxtx";
161        qcom,cmd-crci = <15>;
162        qcom,data-crci = <3>;
163
164        #address-cells = <1>;
165        #size-cells = <0>;
166
167        nand@0 {
168            reg = <0>;
169
170            nand-ecc-strength = <4>;
171            nand-bus-width = <8>;
172
173            qcom,boot-partitions = <0x0 0x58a0000>;
174
175            partitions {
176                compatible = "fixed-partitions";
177                #address-cells = <1>;
178                #size-cells = <1>;
179
180                partition@0 {
181                    label = "boot-nand";
182                    reg = <0 0x58a0000>;
183                };
184
185                partition@58a0000 {
186                    label = "fs-nand";
187                    reg = <0x58a0000 0x4000000>;
188                };
189            };
190        };
191    };
192
193    #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
194    nand-controller@79b0000 {
195        compatible = "qcom,ipq4019-nand";
196        reg = <0x79b0000 0x1000>;
197
198        clocks = <&gcc GCC_QPIC_CLK>,
199                 <&gcc GCC_QPIC_AHB_CLK>;
200        clock-names = "core", "aon";
201
202        dmas = <&qpicbam 0>,
203               <&qpicbam 1>,
204               <&qpicbam 2>;
205        dma-names = "tx", "rx", "cmd";
206
207        #address-cells = <1>;
208        #size-cells = <0>;
209
210        nand@0 {
211            reg = <0>;
212            nand-ecc-strength = <4>;
213            nand-bus-width = <8>;
214
215            partitions {
216                compatible = "fixed-partitions";
217                #address-cells = <1>;
218                #size-cells = <1>;
219
220                partition@0 {
221                    label = "boot-nand";
222                    reg = <0 0x58a0000>;
223                };
224
225                partition@58a0000 {
226                    label = "fs-nand";
227                    reg = <0x58a0000 0x4000000>;
228                };
229            };
230        };
231    };
232
233...
234