1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mtd/nand-controller.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NAND Chip and NAND Controller Generic Binding
8
9maintainers:
10  - Miquel Raynal <miquel.raynal@bootlin.com>
11  - Richard Weinberger <richard@nod.at>
12
13description: |
14  The NAND controller should be represented with its own DT node, and
15  all NAND chips attached to this controller should be defined as
16  children nodes of the NAND controller. This representation should be
17  enforced even for simple controllers supporting only one chip.
18
19  The ECC strength and ECC step size properties define the user
20  desires in terms of correction capability of a controller. Together,
21  they request the ECC engine to correct {strength} bit errors per
22  {size} bytes.
23
24  The interpretation of these parameters is implementation-defined, so
25  not all implementations must support all possible
26  combinations. However, implementations are encouraged to further
27  specify the value(s) they support.
28
29properties:
30  $nodename:
31    pattern: "^nand-controller(@.*)?"
32
33  "#address-cells":
34    const: 1
35
36  "#size-cells":
37    const: 0
38
39  ranges: true
40
41patternProperties:
42  "^nand@[a-f0-9]$":
43    type: object
44    properties:
45      reg:
46        description:
47          Contains the native Ready/Busy IDs.
48
49      nand-ecc-mode:
50        description:
51          Desired ECC engine, either hardware (most of the time
52          embedded in the NAND controller) or software correction
53          (Linux will handle the calculations). soft_bch is deprecated
54          and should be replaced by soft and nand-ecc-algo.
55        $ref: /schemas/types.yaml#/definitions/string
56        enum: [none, soft, hw, hw_syndrome, hw_oob_first, on-die]
57
58      nand-ecc-placement:
59        allOf:
60          - $ref: /schemas/types.yaml#/definitions/string
61          - enum: [ oob, interleaved ]
62        description:
63          Location of the ECC bytes. This location is unknown by default
64          but can be explicitly set to "oob", if all ECC bytes are
65          known to be stored in the OOB area, or "interleaved" if ECC
66          bytes will be interleaved with regular data in the main area.
67
68      nand-ecc-algo:
69        description:
70          Desired ECC algorithm.
71        $ref: /schemas/types.yaml#/definitions/string
72        enum: [hamming, bch, rs]
73
74      nand-bus-width:
75        description:
76          Bus width to the NAND chip
77        $ref: /schemas/types.yaml#/definitions/uint32
78        enum: [8, 16]
79        default: 8
80
81      nand-on-flash-bbt:
82        $ref: /schemas/types.yaml#/definitions/flag
83        description:
84          With this property, the OS will search the device for a Bad
85          Block Table (BBT). If not found, it will create one, reserve
86          a few blocks at the end of the device to store it and update
87          it as the device ages. Otherwise, the out-of-band area of a
88          few pages of all the blocks will be scanned at boot time to
89          find Bad Block Markers (BBM). These markers will help to
90          build a volatile BBT in RAM.
91
92      nand-ecc-strength:
93        description:
94          Maximum number of bits that can be corrected per ECC step.
95        $ref: /schemas/types.yaml#/definitions/uint32
96        minimum: 1
97
98      nand-ecc-step-size:
99        description:
100          Number of data bytes covered by a single ECC step.
101        $ref: /schemas/types.yaml#/definitions/uint32
102        minimum: 1
103
104      nand-ecc-maximize:
105        $ref: /schemas/types.yaml#/definitions/flag
106        description:
107          Whether or not the ECC strength should be maximized. The
108          maximum ECC strength is both controller and chip
109          dependent. The ECC engine has to select the ECC config
110          providing the best strength and taking the OOB area size
111          constraint into account. This is particularly useful when
112          only the in-band area is used by the upper layers, and you
113          want to make your NAND as reliable as possible.
114
115      nand-is-boot-medium:
116        $ref: /schemas/types.yaml#/definitions/flag
117        description:
118          Whether or not the NAND chip is a boot medium. Drivers might
119          use this information to select ECC algorithms supported by
120          the boot ROM or similar restrictions.
121
122      nand-rb:
123        $ref: /schemas/types.yaml#/definitions/uint32-array
124        description:
125          Contains the native Ready/Busy IDs.
126
127      rb-gpios:
128        description:
129          Contains one or more GPIO descriptor (the numper of descriptor
130          depends on the number of R/B pins exposed by the flash) for the
131          Ready/Busy pins. Active state refers to the NAND ready state and
132          should be set to GPIOD_ACTIVE_HIGH unless the signal is inverted.
133
134    required:
135      - reg
136
137required:
138  - "#address-cells"
139  - "#size-cells"
140
141examples:
142  - |
143    nand-controller {
144      #address-cells = <1>;
145      #size-cells = <0>;
146
147      /* controller specific properties */
148
149      nand@0 {
150        reg = <0>;
151        nand-ecc-mode = "soft";
152        nand-ecc-algo = "bch";
153
154        /* controller specific properties */
155      };
156    };
157