1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/mtd/mtd-physmap.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: CFI or JEDEC memory-mapped NOR flash, MTD-RAM (NVRAM...) 8 9maintainers: 10 - Rob Herring <robh@kernel.org> 11 12description: | 13 Flash chips (Memory Technology Devices) are often used for solid state 14 file systems on embedded devices. 15 16properties: 17 compatible: 18 oneOf: 19 - items: 20 - enum: 21 - amd,s29gl01gp 22 - amd,s29gl032a 23 - amd,s29gl256n 24 - amd,s29gl512n 25 - arm,versatile-flash 26 - arm,vexpress-flash 27 - cortina,gemini-flash 28 - cypress,hyperflash 29 - ge,imp3a-firmware-mirror 30 - ge,imp3a-paged-flash 31 - gef,ppc9a-firmware-mirror 32 - gef,ppc9a-paged-flash 33 - gef,sbc310-firmware-mirror 34 - gef,sbc310-paged-flash 35 - gef,sbc610-firmware-mirror 36 - gef,sbc610-paged-flash 37 - intel,28f128j3 38 - intel,dt28f160 39 - intel,ixp4xx-flash 40 - intel,JS28F128 41 - intel,JS28F640 42 - intel,PC28F640P30T85 43 - numonyx,js28f00a 44 - numonyx,js28f128 45 - sst,sst39vf320 46 - xlnx,xps-mch-emc-2.00.a 47 - enum: 48 - cfi-flash 49 - jedec-flash 50 - items: 51 - enum: 52 - cypress,cy7c1019dv33-10zsxi 53 - arm,vexpress-psram 54 - const: mtd-ram 55 - enum: 56 - cfi-flash 57 - jedec-flash 58 - mtd-ram 59 - mtd-rom 60 61 reg: 62 description: | 63 It's possible to (optionally) define multiple "reg" tuples so that 64 non-identical chips can be described in one node. 65 minItems: 1 66 maxItems: 8 67 68 bank-width: 69 description: Width (in bytes) of the bank. Equal to the device width times 70 the number of interleaved chips. 71 $ref: /schemas/types.yaml#/definitions/uint32 72 enum: [ 1, 2, 4 ] 73 74 device-width: 75 description: 76 Width of a single mtd chip. If omitted, assumed to be equal to 'bank-width'. 77 $ref: /schemas/types.yaml#/definitions/uint32 78 enum: [ 1, 2 ] 79 80 no-unaligned-direct-access: 81 type: boolean 82 description: | 83 Disables the default direct mapping of the flash. 84 85 On some platforms (e.g. MPC5200) a direct 1:1 mapping may cause problems 86 with JFFS2 usage, as the local bus (LPB) doesn't support unaligned 87 accesses as implemented in the JFFS2 code via memcpy(). By defining 88 "no-unaligned-direct-access", the flash will not be exposed directly to 89 the MTD users (e.g. JFFS2) any more. 90 91 linux,mtd-name: 92 description: 93 Allows specifying the mtd name for retro capability with physmap-flash 94 drivers as boot loader pass the mtd partition via the old device name 95 physmap-flash. 96 $ref: /schemas/types.yaml#/definitions/string 97 98 use-advanced-sector-protection: 99 type: boolean 100 description: | 101 Enables support for the advanced sector protection (Spansion: PPB - 102 Persistent Protection Bits) locking. 103 104 erase-size: 105 description: The chip's physical erase block size in bytes. 106 $ref: /schemas/types.yaml#/definitions/uint32 107 108 addr-gpios: 109 description: 110 List of GPIO descriptors that will be used to address the MSBs address 111 lines. The order goes from LSB to MSB. 112 minItems: 1 113 maxItems: 8 114 115 '#address-cells': 116 const: 1 117 118 '#size-cells': 119 const: 1 120 121 big-endian: true 122 little-endian: true 123 124patternProperties: 125 '@[0-9a-f]+$': 126 $ref: partitions/partition.yaml 127 128required: 129 - compatible 130 - reg 131 132if: 133 properties: 134 compatible: 135 contains: 136 const: cortina,gemini-flash 137then: 138 properties: 139 syscon: 140 $ref: /schemas/types.yaml#/definitions/phandle 141 description: 142 Phandle to the syscon controller 143 required: 144 - syscon 145 146# FIXME: A parent bus may define timing properties 147additionalProperties: true 148 149examples: 150 - | 151 152 flash@ff000000 { 153 compatible = "cfi-flash"; 154 reg = <0xff000000 0x01000000>; 155 bank-width = <4>; 156 device-width = <1>; 157 158 #address-cells = <1>; 159 #size-cells = <1>; 160 ranges = <0 0xff000000 0x01000000>; 161 162 fs@0 { 163 label = "fs"; 164 reg = <0 0xf80000>; 165 }; 166 firmware@f80000 { 167 label ="firmware"; 168 reg = <0xf80000 0x80000>; 169 read-only; 170 }; 171 }; 172 173 - | 174 /* An example with multiple "reg" tuples */ 175 176 flash@0 { 177 compatible = "intel,PC28F640P30T85", "cfi-flash"; 178 reg = <0x00000000 0x02000000>, 179 <0x02000000 0x02000000>; 180 bank-width = <2>; 181 182 #address-cells = <1>; 183 #size-cells = <1>; 184 ranges = <0 0 0x04000000>; 185 186 partition@0 { 187 label = "test-part1"; 188 reg = <0 0x04000000>; 189 }; 190 }; 191 192 - | 193 /* An example using SRAM */ 194 bus { 195 #address-cells = <2>; 196 #size-cells = <1>; 197 198 sram@2,0 { 199 compatible = "mtd-ram"; 200 reg = <2 0 0x00200000>; 201 bank-width = <2>; 202 }; 203 }; 204 205 - | 206 /* An example using addr-gpios */ 207 #include <dt-bindings/gpio/gpio.h> 208 209 flash@20000000 { 210 compatible = "cfi-flash"; 211 reg = <0x20000000 0x02000000>; 212 bank-width = <2>; 213 addr-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; 214 215 #address-cells = <1>; 216 #size-cells = <1>; 217 ranges = <0 0x00000000 0x02000000>, 218 <1 0x02000000 0x02000000>; 219 220 partition@0 { 221 label = "test-part1"; 222 reg = <0 0x04000000>; 223 }; 224 }; 225... 226