1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mtd/mediatek,nand-ecc-engine.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MediaTek(MTK) SoCs NAND ECC engine
8
9maintainers:
10  - Xiangsheng Hou <xiangsheng.hou@mediatek.com>
11
12description: |
13  MTK NAND ECC engine can cowork with MTK raw NAND and SPI NAND controller.
14
15properties:
16  compatible:
17    enum:
18      - mediatek,mt2701-ecc
19      - mediatek,mt2712-ecc
20      - mediatek,mt7622-ecc
21
22  reg:
23    items:
24      - description: Base physical address and size of ECC.
25
26  interrupts:
27    items:
28      - description: ECC interrupt
29
30  clocks:
31    maxItems: 1
32
33  clock-names:
34    const: nfiecc_clk
35
36required:
37  - compatible
38  - reg
39  - interrupts
40  - clocks
41  - clock-names
42
43additionalProperties: false
44
45examples:
46  - |
47    #include <dt-bindings/clock/mt2701-clk.h>
48    #include <dt-bindings/interrupt-controller/arm-gic.h>
49    #include <dt-bindings/interrupt-controller/irq.h>
50
51    soc {
52        #address-cells = <2>;
53        #size-cells = <2>;
54
55        bch: ecc@1100e000 {
56            compatible = "mediatek,mt2701-ecc";
57            reg = <0 0x1100e000 0 0x1000>;
58            interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
59            clocks = <&pericfg CLK_PERI_NFI_ECC>;
60            clock-names = "nfiecc_clk";
61        };
62    };
63