1*3af7ade2SXiangsheng Hou# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*3af7ade2SXiangsheng Hou%YAML 1.2 3*3af7ade2SXiangsheng Hou--- 4*3af7ade2SXiangsheng Hou$id: http://devicetree.org/schemas/mtd/mediatek,nand-ecc-engine.yaml# 5*3af7ade2SXiangsheng Hou$schema: http://devicetree.org/meta-schemas/core.yaml# 6*3af7ade2SXiangsheng Hou 7*3af7ade2SXiangsheng Houtitle: MediaTek(MTK) SoCs NAND ECC engine 8*3af7ade2SXiangsheng Hou 9*3af7ade2SXiangsheng Houmaintainers: 10*3af7ade2SXiangsheng Hou - Xiangsheng Hou <xiangsheng.hou@mediatek.com> 11*3af7ade2SXiangsheng Hou 12*3af7ade2SXiangsheng Houdescription: | 13*3af7ade2SXiangsheng Hou MTK NAND ECC engine can cowork with MTK raw NAND and SPI NAND controller. 14*3af7ade2SXiangsheng Hou 15*3af7ade2SXiangsheng Houproperties: 16*3af7ade2SXiangsheng Hou compatible: 17*3af7ade2SXiangsheng Hou enum: 18*3af7ade2SXiangsheng Hou - mediatek,mt2701-ecc 19*3af7ade2SXiangsheng Hou - mediatek,mt2712-ecc 20*3af7ade2SXiangsheng Hou - mediatek,mt7622-ecc 21*3af7ade2SXiangsheng Hou 22*3af7ade2SXiangsheng Hou reg: 23*3af7ade2SXiangsheng Hou items: 24*3af7ade2SXiangsheng Hou - description: Base physical address and size of ECC. 25*3af7ade2SXiangsheng Hou 26*3af7ade2SXiangsheng Hou interrupts: 27*3af7ade2SXiangsheng Hou items: 28*3af7ade2SXiangsheng Hou - description: ECC interrupt 29*3af7ade2SXiangsheng Hou 30*3af7ade2SXiangsheng Hou clocks: 31*3af7ade2SXiangsheng Hou maxItems: 1 32*3af7ade2SXiangsheng Hou 33*3af7ade2SXiangsheng Hou clock-names: 34*3af7ade2SXiangsheng Hou const: nfiecc_clk 35*3af7ade2SXiangsheng Hou 36*3af7ade2SXiangsheng Hourequired: 37*3af7ade2SXiangsheng Hou - compatible 38*3af7ade2SXiangsheng Hou - reg 39*3af7ade2SXiangsheng Hou - interrupts 40*3af7ade2SXiangsheng Hou - clocks 41*3af7ade2SXiangsheng Hou - clock-names 42*3af7ade2SXiangsheng Hou 43*3af7ade2SXiangsheng HouadditionalProperties: false 44*3af7ade2SXiangsheng Hou 45*3af7ade2SXiangsheng Houexamples: 46*3af7ade2SXiangsheng Hou - | 47*3af7ade2SXiangsheng Hou #include <dt-bindings/clock/mt2701-clk.h> 48*3af7ade2SXiangsheng Hou #include <dt-bindings/interrupt-controller/arm-gic.h> 49*3af7ade2SXiangsheng Hou #include <dt-bindings/interrupt-controller/irq.h> 50*3af7ade2SXiangsheng Hou 51*3af7ade2SXiangsheng Hou soc { 52*3af7ade2SXiangsheng Hou #address-cells = <2>; 53*3af7ade2SXiangsheng Hou #size-cells = <2>; 54*3af7ade2SXiangsheng Hou 55*3af7ade2SXiangsheng Hou bch: ecc@1100e000 { 56*3af7ade2SXiangsheng Hou compatible = "mediatek,mt2701-ecc"; 57*3af7ade2SXiangsheng Hou reg = <0 0x1100e000 0 0x1000>; 58*3af7ade2SXiangsheng Hou interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>; 59*3af7ade2SXiangsheng Hou clocks = <&pericfg CLK_PERI_NFI_ECC>; 60*3af7ade2SXiangsheng Hou clock-names = "nfiecc_clk"; 61*3af7ade2SXiangsheng Hou }; 62*3af7ade2SXiangsheng Hou }; 63