1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mtd/ingenic,nand.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Ingenic SoCs NAND controller devicetree bindings
8
9maintainers:
10  - Paul Cercueil <paul@crapouillou.net>
11
12allOf:
13  - $ref: nand-controller.yaml#
14
15properties:
16  compatible:
17    enum:
18      - ingenic,jz4740-nand
19      - ingenic,jz4725b-nand
20      - ingenic,jz4780-nand
21
22  reg:
23    items:
24      - description: Bank number, offset and size of first attached NAND chip
25      - description: Bank number, offset and size of second attached NAND chip
26      - description: Bank number, offset and size of third attached NAND chip
27      - description: Bank number, offset and size of fourth attached NAND chip
28    minItems: 1
29
30  ecc-engine: true
31
32  partitions:
33    type: object
34    description:
35      Node containing description of fixed partitions.
36      See Documentation/devicetree/bindings/mtd/partition.txt
37
38patternProperties:
39  "^nand@[a-f0-9]$":
40    type: object
41    properties:
42      rb-gpios:
43        description: GPIO specifier for the busy pin.
44        maxItems: 1
45
46      wp-gpios:
47        description: GPIO specifier for the write-protect pin.
48        maxItems: 1
49
50required:
51  - compatible
52  - reg
53
54unevaluatedProperties: false
55
56examples:
57  - |
58    #include <dt-bindings/clock/ingenic,jz4780-cgu.h>
59    memory-controller@13410000 {
60      compatible = "ingenic,jz4780-nemc";
61      reg = <0x13410000 0x10000>;
62      #address-cells = <2>;
63      #size-cells = <1>;
64      ranges = <1 0 0x1b000000 0x1000000>,
65         <2 0 0x1a000000 0x1000000>,
66         <3 0 0x19000000 0x1000000>,
67         <4 0 0x18000000 0x1000000>,
68         <5 0 0x17000000 0x1000000>,
69         <6 0 0x16000000 0x1000000>;
70
71      clocks = <&cgu JZ4780_CLK_NEMC>;
72
73      nand-controller@1 {
74        compatible = "ingenic,jz4780-nand";
75        reg = <1 0 0x1000000>;
76
77        #address-cells = <1>;
78        #size-cells = <0>;
79
80        ecc-engine = <&bch>;
81
82        ingenic,nemc-tAS = <10>;
83        ingenic,nemc-tAH = <5>;
84        ingenic,nemc-tBP = <10>;
85        ingenic,nemc-tAW = <15>;
86        ingenic,nemc-tSTRV = <100>;
87
88        pinctrl-names = "default";
89        pinctrl-0 = <&pins_nemc>;
90
91        nand@1 {
92          reg = <1>;
93
94          nand-ecc-step-size = <1024>;
95          nand-ecc-strength = <24>;
96          nand-ecc-mode = "hw";
97          nand-on-flash-bbt;
98
99          pinctrl-names = "default";
100          pinctrl-0 = <&pins_nemc_cs1>;
101
102          partitions {
103            compatible = "fixed-partitions";
104            #address-cells = <2>;
105            #size-cells = <2>;
106
107            partition@0 {
108              label = "u-boot-spl";
109              reg = <0x0 0x0 0x0 0x800000>;
110            };
111
112            partition@800000 {
113              label = "u-boot";
114              reg = <0x0 0x800000 0x0 0x200000>;
115            };
116
117            partition@a00000 {
118              label = "u-boot-env";
119              reg = <0x0 0xa00000 0x0 0x200000>;
120            };
121
122            partition@c00000 {
123              label = "boot";
124              reg = <0x0 0xc00000 0x0 0x4000000>;
125            };
126
127            partition@4c00000 {
128              label = "system";
129              reg = <0x0 0x4c00000 0x1 0xfb400000>;
130            };
131          };
132        };
133      };
134    };
135