1775c3220SJamie IlesGPIO assisted NAND flash 2775c3220SJamie Iles 3775c3220SJamie IlesThe GPIO assisted NAND flash uses a memory mapped interface to 4775c3220SJamie Ilesread/write the NAND commands and data and GPIO pins for the control 5775c3220SJamie Ilessignals. 6775c3220SJamie Iles 7775c3220SJamie IlesRequired properties: 8775c3220SJamie Iles- compatible : "gpio-control-nand" 9775c3220SJamie Iles- reg : should specify localbus chip select and size used for the chip. The 10775c3220SJamie Iles resource describes the data bus connected to the NAND flash and all accesses 11775c3220SJamie Iles are made in native endianness. 12775c3220SJamie Iles- #address-cells, #size-cells : Must be present if the device has sub-nodes 13775c3220SJamie Iles representing partitions. 14775c3220SJamie Iles- gpios : specifies the gpio pins to control the NAND device. nwp is an 15775c3220SJamie Iles optional gpio and may be set to 0 if not present. 16775c3220SJamie Iles 17775c3220SJamie IlesOptional properties: 18775c3220SJamie Iles- bank-width : Width (in bytes) of the device. If not present, the width 19775c3220SJamie Iles defaults to 1 byte. 20775c3220SJamie Iles- chip-delay : chip dependent delay for transferring data from array to 21775c3220SJamie Iles read registers (tR). If not present then a default of 20us is used. 22775c3220SJamie Iles- gpio-control-nand,io-sync-reg : A 64-bit physical address for a read 23775c3220SJamie Iles location used to guard against bus reordering with regards to accesses to 24775c3220SJamie Iles the GPIO's and the NAND flash data bus. If present, then after changing 25775c3220SJamie Iles GPIO state and before and after command byte writes, this register will be 26775c3220SJamie Iles read to ensure that the GPIO accesses have completed. 27775c3220SJamie Iles 2883619ea0SJamie LentinThe device tree may optionally contain sub-nodes describing partitions of the 2983619ea0SJamie Lentinaddress space. See partition.txt for more detail. 3083619ea0SJamie Lentin 31775c3220SJamie IlesExamples: 32775c3220SJamie Iles 33775c3220SJamie Ilesgpio-nand@1,0 { 34775c3220SJamie Iles compatible = "gpio-control-nand"; 35775c3220SJamie Iles reg = <1 0x0000 0x2>; 36775c3220SJamie Iles #address-cells = <1>; 37775c3220SJamie Iles #size-cells = <1>; 38775c3220SJamie Iles gpios = <&banka 1 0 /* rdy */ 39775c3220SJamie Iles &banka 2 0 /* nce */ 40775c3220SJamie Iles &banka 3 0 /* ale */ 41775c3220SJamie Iles &banka 4 0 /* cle */ 42775c3220SJamie Iles 0 /* nwp */>; 43775c3220SJamie Iles 44775c3220SJamie Iles partition@0 { 45775c3220SJamie Iles ... 46775c3220SJamie Iles }; 47775c3220SJamie Iles}; 48