1Freescale Localbus UPM programmed to work with NAND flash
2
3Required properties:
4- compatible : "fsl,upm-nand".
5- reg : should specify localbus chip select and size used for the chip.
6- fsl,upm-addr-offset : UPM pattern offset for the address latch.
7- fsl,upm-cmd-offset : UPM pattern offset for the command latch.
8
9Optional properties:
10- fsl,upm-wait-flags : add chip-dependent short delays after running the
11	UPM pattern (0x1), after writing a data byte (0x2) or after
12	writing out a buffer (0x4).
13- fsl,upm-addr-line-cs-offsets : address offsets for multi-chip support.
14	The corresponding address lines are used to select the chip.
15- gpios : may specify optional GPIOs connected to the Ready-Not-Busy pins
16	(R/B#). For multi-chip devices, "n" GPIO definitions are required
17	according to the number of chips.
18- chip-delay : chip dependent delay for transfering data from array to
19	read registers (tR). Required if property "gpios" is not used
20	(R/B# pins not connected).
21
22Examples:
23
24upm@1,0 {
25	compatible = "fsl,upm-nand";
26	reg = <1 0 1>;
27	fsl,upm-addr-offset = <16>;
28	fsl,upm-cmd-offset = <8>;
29	gpios = <&qe_pio_e 18 0>;
30
31	flash {
32		#address-cells = <1>;
33		#size-cells = <1>;
34		compatible = "...";
35
36		partition@0 {
37			...
38		};
39	};
40};
41
42upm@3,0 {
43	#address-cells = <0>;
44	#size-cells = <0>;
45	compatible = "tqc,tqm8548-upm-nand", "fsl,upm-nand";
46	reg = <3 0x0 0x800>;
47	fsl,upm-addr-offset = <0x10>;
48	fsl,upm-cmd-offset = <0x08>;
49	/* Multi-chip NAND device */
50	fsl,upm-addr-line-cs-offsets = <0x0 0x200>;
51	fsl,upm-wait-flags = <0x5>;
52	chip-delay = <25>; // in micro-seconds
53
54	nand@0 {
55		#address-cells = <1>;
56		#size-cells = <1>;
57
58		partition@0 {
59			    label = "fs";
60			    reg = <0x00000000 0x10000000>;
61		};
62	};
63};
64