1Atmel NAND flash controller bindings
2
3The NAND flash controller node should be defined under the EBI bus (see
4Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt).
5One or several NAND devices can be defined under this NAND controller.
6The NAND controller might be connected to an ECC engine.
7
8* NAND controller bindings:
9
10Required properties:
11- compatible: should be one of the following
12	"atmel,at91rm9200-nand-controller"
13	"atmel,at91sam9260-nand-controller"
14	"atmel,at91sam9261-nand-controller"
15	"atmel,at91sam9g45-nand-controller"
16	"atmel,sama5d3-nand-controller"
17- ranges: empty ranges property to forward EBI ranges definitions.
18- #address-cells: should be set to 2.
19- #size-cells: should be set to 1.
20- atmel,nfc-io: phandle to the NFC IO block. Only required for sama5d3
21		controllers.
22- atmel,nfc-sram: phandle to the NFC SRAM block. Only required for sama5d3
23		  controllers.
24
25Optional properties:
26- ecc-engine: phandle to the PMECC block. Only meaningful if the SoC embeds
27	      a PMECC engine.
28
29* NAND device/chip bindings:
30
31Required properties:
32- reg: describes the CS lines assigned to the NAND device. If the NAND device
33       exposes multiple CS lines (multi-dies chips), your reg property will
34       contain X tuples of 3 entries.
35       1st entry: the CS line this NAND chip is connected to
36       2nd entry: the base offset of the memory region assigned to this
37		  device (always 0)
38       3rd entry: the memory region size (always 0x800000)
39
40Optional properties:
41- rb-gpios: the GPIO(s) used to check the Ready/Busy status of the NAND.
42- cs-gpios: the GPIO(s) used to control the CS line.
43- det-gpios: the GPIO used to detect if a Smartmedia Card is present.
44- atmel,rb: an integer identifying the native Ready/Busy pin. Only meaningful
45	    on sama5 SoCs.
46
47All generic properties described in
48Documentation/devicetree/bindings/mtd/{common,nand}.txt also apply to the NAND
49device node, and NAND partitions should be defined under the NAND node as
50described in Documentation/devicetree/bindings/mtd/partition.txt.
51
52* ECC engine (PMECC) bindings:
53
54Required properties:
55- compatible: should be one of the following
56	"atmel,at91sam9g45-pmecc"
57	"atmel,sama5d4-pmecc"
58	"atmel,sama5d2-pmecc"
59- reg: should contain 2 register ranges. The first one is pointing to the PMECC
60       block, and the second one to the PMECC_ERRLOC block.
61
62Example:
63
64	pmecc: ecc-engine@ffffc070 {
65		compatible = "atmel,at91sam9g45-pmecc";
66                reg = <0xffffc070 0x490>,
67                      <0xffffc500 0x100>;
68	};
69
70	ebi: ebi@10000000 {
71		compatible = "atmel,sama5d3-ebi";
72		#address-cells = <2>;
73		#size-cells = <1>;
74		atmel,smc = <&hsmc>;
75		reg = <0x10000000 0x10000000
76		       0x40000000 0x30000000>;
77		ranges = <0x0 0x0 0x10000000 0x10000000
78			  0x1 0x0 0x40000000 0x10000000
79			  0x2 0x0 0x50000000 0x10000000
80			  0x3 0x0 0x60000000 0x10000000>;
81		clocks = <&mck>;
82
83                nand_controller: nand-controller {
84			compatible = "atmel,sama5d3-nand-controller";
85			atmel,nfc-sram = <&nfc_sram>;
86			atmel,nfc-io = <&nfc_io>;
87			ecc-engine = <&pmecc>;
88			#address-cells = <2>;
89			#size-cells = <1>;
90			ranges;
91
92			nand@3 {
93				reg = <0x3 0x0 0x800000>;
94				atmel,rb = <0>;
95
96				/*
97				 * Put generic NAND/MTD properties and
98				 * subnodes here.
99				 */
100			};
101		};
102	};
103
104-----------------------------------------------------------------------
105
106Deprecated bindings (should not be used in new device trees):
107
108Required properties:
109- compatible: The possible values are:
110	"atmel,at91rm9200-nand"
111	"atmel,sama5d2-nand"
112	"atmel,sama5d4-nand"
113- reg : should specify localbus address and size used for the chip,
114	and hardware ECC controller if available.
115	If the hardware ECC is PMECC, it should contain address and size for
116	PMECC and PMECC Error Location controller.
117	The PMECC lookup table address and size in ROM is optional. If not
118	specified, driver will build it in runtime.
119- atmel,nand-addr-offset : offset for the address latch.
120- atmel,nand-cmd-offset : offset for the command latch.
121- #address-cells, #size-cells : Must be present if the device has sub-nodes
122  representing partitions.
123
124- gpios : specifies the gpio pins to control the NAND device. detect is an
125  optional gpio and may be set to 0 if not present.
126
127Optional properties:
128- atmel,nand-has-dma : boolean to support dma transfer for nand read/write.
129- nand-ecc-mode : String, operation mode of the NAND ecc mode, soft by default.
130  Supported values are: "none", "soft", "hw", "hw_syndrome", "hw_oob_first",
131  "soft_bch".
132- atmel,has-pmecc : boolean to enable Programmable Multibit ECC hardware,
133  capable of BCH encoding and decoding, on devices where it is present.
134- atmel,pmecc-cap : error correct capability for Programmable Multibit ECC
135  Controller. Supported values are: 2, 4, 8, 12, 24. If the compatible string
136  is "atmel,sama5d2-nand", 32 is also valid.
137- atmel,pmecc-sector-size : sector size for ECC computation. Supported values
138  are: 512, 1024.
139- atmel,pmecc-lookup-table-offset : includes two offsets of lookup table in ROM
140  for different sector size. First one is for sector size 512, the next is for
141  sector size 1024. If not specified, driver will build the table in runtime.
142- nand-bus-width : 8 or 16 bus width if not present 8
143- nand-on-flash-bbt: boolean to enable on flash bbt option if not present false
144
145Nand Flash Controller(NFC) is an optional sub-node
146Required properties:
147- compatible : "atmel,sama5d3-nfc".
148- reg : should specify the address and size used for NFC command registers,
149        NFC registers and NFC SRAM. NFC SRAM address and size can be absent
150        if don't want to use it.
151- clocks: phandle to the peripheral clock
152Optional properties:
153- atmel,write-by-sram: boolean to enable NFC write by SRAM.
154
155Examples:
156nand0: nand@40000000,0 {
157	compatible = "atmel,at91rm9200-nand";
158	#address-cells = <1>;
159	#size-cells = <1>;
160	reg = <0x40000000 0x10000000
161	       0xffffe800 0x200
162	      >;
163	atmel,nand-addr-offset = <21>;	/* ale */
164	atmel,nand-cmd-offset = <22>;	/* cle */
165	nand-on-flash-bbt;
166	nand-ecc-mode = "soft";
167	gpios = <&pioC 13 0	/* rdy */
168		 &pioC 14 0 	/* nce */
169		 0		/* cd */
170		>;
171	partition@0 {
172		...
173	};
174};
175
176/* for PMECC supported chips */
177nand0: nand@40000000 {
178	compatible = "atmel,at91rm9200-nand";
179	#address-cells = <1>;
180	#size-cells = <1>;
181	reg = < 0x40000000 0x10000000	/* bus addr & size */
182		0xffffe000 0x00000600	/* PMECC addr & size */
183		0xffffe600 0x00000200	/* PMECC ERRLOC addr & size */
184		0x00100000 0x00100000	/* ROM addr & size */
185		>;
186	atmel,nand-addr-offset = <21>;	/* ale */
187	atmel,nand-cmd-offset = <22>;	/* cle */
188	nand-on-flash-bbt;
189	nand-ecc-mode = "hw";
190	atmel,has-pmecc;	/* enable PMECC */
191	atmel,pmecc-cap = <2>;
192	atmel,pmecc-sector-size = <512>;
193	atmel,pmecc-lookup-table-offset = <0x8000 0x10000>;
194	gpios = <&pioD 5 0	/* rdy */
195		 &pioD 4 0	/* nce */
196		 0		/* cd */
197		>;
198	partition@0 {
199		...
200	};
201};
202
203/* for NFC supported chips */
204nand0: nand@40000000 {
205	compatible = "atmel,at91rm9200-nand";
206	#address-cells = <1>;
207	#size-cells = <1>;
208	ranges;
209        ...
210        nfc@70000000 {
211		compatible = "atmel,sama5d3-nfc";
212		#address-cells = <1>;
213		#size-cells = <1>;
214		clocks = <&hsmc_clk>
215		reg = <
216			0x70000000 0x10000000	/* NFC Command Registers */
217			0xffffc000 0x00000070	/* NFC HSMC regs */
218			0x00200000 0x00100000	/* NFC SRAM banks */
219		>;
220	};
221};
222