1# SPDX-License-Identifier: GPL-2.0-only
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mmc/snps,dwcmshc-sdhci.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Synopsys Designware Mobile Storage Host Controller Binding
8
9maintainers:
10  - Ulf Hansson <ulf.hansson@linaro.org>
11  - Jisheng Zhang <Jisheng.Zhang@synaptics.com>
12
13allOf:
14  - $ref: mmc-controller.yaml#
15
16properties:
17  compatible:
18    enum:
19      - rockchip,rk3568-dwcmshc
20      - snps,dwcmshc-sdhci
21
22  reg:
23    maxItems: 1
24
25  interrupts:
26    maxItems: 1
27
28  clocks:
29    minItems: 1
30    items:
31      - description: core clock
32      - description: bus clock for optional
33      - description: axi clock for rockchip specified
34      - description: block clock for rockchip specified
35      - description: timer clock for rockchip specified
36
37
38  clock-names:
39    minItems: 1
40    items:
41      - const: core
42      - const: bus
43      - const: axi
44      - const: block
45      - const: timer
46
47  rockchip,txclk-tapnum:
48    description: Specify the number of delay for tx sampling.
49    $ref: /schemas/types.yaml#/definitions/uint8
50
51
52required:
53  - compatible
54  - reg
55  - interrupts
56  - clocks
57  - clock-names
58
59unevaluatedProperties: false
60
61examples:
62  - |
63    mmc@fe310000 {
64      compatible = "rockchip,rk3568-dwcmshc";
65      reg = <0xfe310000 0x10000>;
66      interrupts = <0 25 0x4>;
67      clocks = <&cru 17>, <&cru 18>, <&cru 19>, <&cru 20>, <&cru 21>;
68      clock-names = "core", "bus", "axi", "block", "timer";
69      bus-width = <8>;
70      #address-cells = <1>;
71      #size-cells = <0>;
72    };
73  - |
74    mmc@aa0000 {
75      compatible = "snps,dwcmshc-sdhci";
76      reg = <0xaa000 0x1000>;
77      interrupts = <0 25 0x4>;
78      clocks = <&cru 17>, <&cru 18>;
79      clock-names = "core", "bus";
80      bus-width = <8>;
81      #address-cells = <1>;
82      #size-cells = <0>;
83    };
84
85...
86