1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mmc/sdhci-msm.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SDHCI controller (sdhci-msm)
8
9maintainers:
10  - Bhupesh Sharma <bhupesh.sharma@linaro.org>
11
12description:
13  Secure Digital Host Controller Interface (SDHCI) present on
14  Qualcomm SOCs supports SD/MMC/SDIO devices.
15
16properties:
17  compatible:
18    oneOf:
19      - enum:
20          - qcom,sdhci-msm-v4
21        deprecated: true
22      - items:
23          - enum:
24              - qcom,apq8084-sdhci
25              - qcom,msm8226-sdhci
26              - qcom,msm8953-sdhci
27              - qcom,msm8974-sdhci
28              - qcom,msm8976-sdhci
29              - qcom,msm8916-sdhci
30              - qcom,msm8992-sdhci
31              - qcom,msm8994-sdhci
32              - qcom,msm8996-sdhci
33              - qcom,msm8998-sdhci
34          - const: qcom,sdhci-msm-v4 # for sdcc versions less than 5.0
35      - items:
36          - enum:
37              - qcom,qcs404-sdhci
38              - qcom,sc7180-sdhci
39              - qcom,sc7280-sdhci
40              - qcom,sdm630-sdhci
41              - qcom,sdm670-sdhci
42              - qcom,sdm845-sdhci
43              - qcom,sdx55-sdhci
44              - qcom,sdx65-sdhci
45              - qcom,sm6115-sdhci
46              - qcom,sm6125-sdhci
47              - qcom,sm6350-sdhci
48              - qcom,sm6375-sdhci
49              - qcom,sm8150-sdhci
50              - qcom,sm8250-sdhci
51              - qcom,sm8350-sdhci
52              - qcom,sm8450-sdhci
53              - qcom,sm8550-sdhci
54          - const: qcom,sdhci-msm-v5 # for sdcc version 5.0
55
56  reg:
57    minItems: 1
58    maxItems: 4
59
60  reg-names:
61    minItems: 1
62    maxItems: 4
63
64  clocks:
65    minItems: 3
66    items:
67      - description: Main peripheral bus clock, PCLK/HCLK - AHB Bus clock
68      - description: SDC MMC clock, MCLK
69      - description: TCXO clock
70      - description: clock for Inline Crypto Engine
71      - description: SDCC bus voter clock
72      - description: reference clock for RCLK delay calibration
73      - description: sleep clock for RCLK delay calibration
74
75  clock-names:
76    minItems: 2
77    items:
78      - const: iface
79      - const: core
80      - const: xo
81      - const: ice
82      - const: bus
83      - const: cal
84      - const: sleep
85
86  dma-coherent: true
87
88  interrupts:
89    maxItems: 2
90
91  interrupt-names:
92    items:
93      - const: hc_irq
94      - const: pwr_irq
95
96  pinctrl-names:
97    minItems: 1
98    items:
99      - const: default
100      - const: sleep
101
102  pinctrl-0:
103    description:
104      Should specify pin control groups used for this controller.
105
106  pinctrl-1:
107    description:
108      Should specify sleep pin control groups used for this controller.
109
110  resets:
111    maxItems: 1
112
113  qcom,ddr-config:
114    $ref: /schemas/types.yaml#/definitions/uint32
115    description: platform specific settings for DDR_CONFIG reg.
116
117  qcom,dll-config:
118    $ref: /schemas/types.yaml#/definitions/uint32
119    description: platform specific settings for DLL_CONFIG reg.
120
121  iommus:
122    minItems: 1
123    maxItems: 8
124    description: |
125      phandle to apps_smmu node with sid mask.
126
127  interconnects:
128    items:
129      - description: data path, sdhc to ddr
130      - description: config path, cpu to sdhc
131
132  interconnect-names:
133    items:
134      - const: sdhc-ddr
135      - const: cpu-sdhc
136
137  power-domains:
138    description: A phandle to sdhci power domain node
139    maxItems: 1
140
141  operating-points-v2: true
142
143patternProperties:
144  '^opp-table(-[a-z0-9]+)?$':
145    if:
146      properties:
147        compatible:
148          const: operating-points-v2
149    then:
150      patternProperties:
151        '^opp-?[0-9]+$':
152          required:
153            - required-opps
154
155required:
156  - compatible
157  - reg
158  - clocks
159  - clock-names
160  - interrupts
161
162allOf:
163  - $ref: sdhci-common.yaml#
164
165  - if:
166      properties:
167        compatible:
168          contains:
169            enum:
170              - qcom,sdhci-msm-v4
171    then:
172      properties:
173        reg:
174          minItems: 2
175          items:
176            - description: Host controller register map
177            - description: SD Core register map
178            - description: CQE register map
179            - description: Inline Crypto Engine register map
180        reg-names:
181          minItems: 2
182          items:
183            - const: hc
184            - const: core
185            - const: cqhci
186            - const: ice
187    else:
188      properties:
189        reg:
190          minItems: 1
191          items:
192            - description: Host controller register map
193            - description: CQE register map
194            - description: Inline Crypto Engine register map
195        reg-names:
196          minItems: 1
197          items:
198            - const: hc
199            - const: cqhci
200            - const: ice
201
202unevaluatedProperties: false
203
204examples:
205  - |
206    #include <dt-bindings/interrupt-controller/arm-gic.h>
207    #include <dt-bindings/clock/qcom,gcc-sm8250.h>
208    #include <dt-bindings/clock/qcom,rpmh.h>
209    #include <dt-bindings/power/qcom-rpmpd.h>
210
211    sdhc_2: mmc@8804000 {
212      compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5";
213      reg = <0 0x08804000 0 0x1000>;
214
215      interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
216                   <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
217      interrupt-names = "hc_irq", "pwr_irq";
218
219      clocks = <&gcc GCC_SDCC2_AHB_CLK>,
220               <&gcc GCC_SDCC2_APPS_CLK>,
221               <&rpmhcc RPMH_CXO_CLK>;
222      clock-names = "iface", "core", "xo";
223      iommus = <&apps_smmu 0x4a0 0x0>;
224      qcom,dll-config = <0x0007642c>;
225      qcom,ddr-config = <0x80040868>;
226      power-domains = <&rpmhpd SM8250_CX>;
227
228      operating-points-v2 = <&sdhc2_opp_table>;
229
230      sdhc2_opp_table: opp-table {
231        compatible = "operating-points-v2";
232
233        opp-19200000 {
234          opp-hz = /bits/ 64 <19200000>;
235          required-opps = <&rpmhpd_opp_min_svs>;
236        };
237
238        opp-50000000 {
239          opp-hz = /bits/ 64 <50000000>;
240          required-opps = <&rpmhpd_opp_low_svs>;
241        };
242
243        opp-100000000 {
244          opp-hz = /bits/ 64 <100000000>;
245          required-opps = <&rpmhpd_opp_svs>;
246        };
247
248        opp-202000000 {
249          opp-hz = /bits/ 64 <202000000>;
250          required-opps = <&rpmhpd_opp_svs_l1>;
251        };
252      };
253    };
254