1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
3%YAML 1.2
4---
5$id: "http://devicetree.org/schemas/mmc/sdhci-msm.yaml#"
6$schema: "http://devicetree.org/meta-schemas/core.yaml#"
7
8title: Qualcomm SDHCI controller (sdhci-msm)
9
10maintainers:
11  - Bhupesh Sharma <bhupesh.sharma@linaro.org>
12
13description:
14  Secure Digital Host Controller Interface (SDHCI) present on
15  Qualcomm SOCs supports SD/MMC/SDIO devices.
16
17properties:
18  compatible:
19    oneOf:
20      - enum:
21          - qcom,sdhci-msm-v4
22        deprecated: true
23      - items:
24          - enum:
25              - qcom,apq8084-sdhci
26              - qcom,msm8226-sdhci
27              - qcom,msm8953-sdhci
28              - qcom,msm8974-sdhci
29              - qcom,msm8916-sdhci
30              - qcom,msm8992-sdhci
31              - qcom,msm8994-sdhci
32              - qcom,msm8996-sdhci
33              - qcom,msm8998-sdhci
34          - const: qcom,sdhci-msm-v4 # for sdcc versions less than 5.0
35      - items:
36          - enum:
37              - qcom,qcs404-sdhci
38              - qcom,sc7180-sdhci
39              - qcom,sc7280-sdhci
40              - qcom,sdm630-sdhci
41              - qcom,sdm845-sdhci
42              - qcom,sdx55-sdhci
43              - qcom,sdx65-sdhci
44              - qcom,sm6125-sdhci
45              - qcom,sm6350-sdhci
46              - qcom,sm8150-sdhci
47              - qcom,sm8250-sdhci
48              - qcom,sm8450-sdhci
49          - const: qcom,sdhci-msm-v5 # for sdcc version 5.0
50
51  reg:
52    minItems: 1
53    maxItems: 4
54
55  reg-names:
56    minItems: 1
57    maxItems: 4
58
59  clocks:
60    minItems: 3
61    items:
62      - description: Main peripheral bus clock, PCLK/HCLK - AHB Bus clock
63      - description: SDC MMC clock, MCLK
64      - description: TCXO clock
65      - description: clock for Inline Crypto Engine
66      - description: SDCC bus voter clock
67      - description: reference clock for RCLK delay calibration
68      - description: sleep clock for RCLK delay calibration
69
70  clock-names:
71    minItems: 2
72    items:
73      - const: iface
74      - const: core
75      - const: xo
76      - const: ice
77      - const: bus
78      - const: cal
79      - const: sleep
80
81  interrupts:
82    maxItems: 2
83
84  interrupt-names:
85    items:
86      - const: hc_irq
87      - const: pwr_irq
88
89  pinctrl-names:
90    minItems: 1
91    items:
92      - const: default
93      - const: sleep
94
95  pinctrl-0:
96    description:
97      Should specify pin control groups used for this controller.
98
99  resets:
100    maxItems: 1
101
102  qcom,ddr-config:
103    $ref: /schemas/types.yaml#/definitions/uint32
104    description: platform specific settings for DDR_CONFIG reg.
105
106  qcom,dll-config:
107    $ref: /schemas/types.yaml#/definitions/uint32
108    description: platform specific settings for DLL_CONFIG reg.
109
110  iommus:
111    minItems: 1
112    maxItems: 8
113    description: |
114      phandle to apps_smmu node with sid mask.
115
116  interconnects:
117    items:
118      - description: data path, sdhc to ddr
119      - description: config path, cpu to sdhc
120
121  interconnect-names:
122    items:
123      - const: sdhc-ddr
124      - const: cpu-sdhc
125
126  power-domains:
127    description: A phandle to sdhci power domain node
128    maxItems: 1
129
130  mmc-ddr-1_8v: true
131
132  mmc-hs200-1_8v: true
133
134  mmc-hs400-1_8v: true
135
136  bus-width: true
137
138  max-frequency: true
139
140patternProperties:
141  '^opp-table(-[a-z0-9]+)?$':
142    if:
143      properties:
144        compatible:
145          const: operating-points-v2
146    then:
147      patternProperties:
148        '^opp-?[0-9]+$':
149          required:
150            - required-opps
151
152required:
153  - compatible
154  - reg
155  - clocks
156  - clock-names
157  - interrupts
158
159allOf:
160  - $ref: mmc-controller.yaml#
161
162  - if:
163      properties:
164        compatible:
165          contains:
166            enum:
167              - qcom,sdhci-msm-v4
168    then:
169      properties:
170        reg:
171          minItems: 2
172          items:
173            - description: Host controller register map
174            - description: SD Core register map
175            - description: CQE register map
176            - description: Inline Crypto Engine register map
177        reg-names:
178          minItems: 2
179          items:
180            - const: hc
181            - const: core
182            - const: cqhci
183            - const: ice
184    else:
185      properties:
186        reg:
187          minItems: 1
188          items:
189            - description: Host controller register map
190            - description: CQE register map
191            - description: Inline Crypto Engine register map
192        reg-names:
193          minItems: 1
194          items:
195            - const: hc
196            - const: cqhci
197            - const: ice
198
199unevaluatedProperties: false
200
201examples:
202  - |
203    #include <dt-bindings/interrupt-controller/arm-gic.h>
204    #include <dt-bindings/clock/qcom,gcc-sm8250.h>
205    #include <dt-bindings/clock/qcom,rpmh.h>
206    #include <dt-bindings/power/qcom-rpmpd.h>
207
208    sdhc_2: mmc@8804000 {
209      compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5";
210      reg = <0 0x08804000 0 0x1000>;
211
212      interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
213                   <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
214      interrupt-names = "hc_irq", "pwr_irq";
215
216      clocks = <&gcc GCC_SDCC2_AHB_CLK>,
217               <&gcc GCC_SDCC2_APPS_CLK>,
218               <&rpmhcc RPMH_CXO_CLK>;
219      clock-names = "iface", "core", "xo";
220      iommus = <&apps_smmu 0x4a0 0x0>;
221      qcom,dll-config = <0x0007642c>;
222      qcom,ddr-config = <0x80040868>;
223      power-domains = <&rpmhpd SM8250_CX>;
224
225      operating-points-v2 = <&sdhc2_opp_table>;
226
227      sdhc2_opp_table: opp-table {
228        compatible = "operating-points-v2";
229
230        opp-19200000 {
231          opp-hz = /bits/ 64 <19200000>;
232          required-opps = <&rpmhpd_opp_min_svs>;
233        };
234
235        opp-50000000 {
236          opp-hz = /bits/ 64 <50000000>;
237          required-opps = <&rpmhpd_opp_low_svs>;
238        };
239
240        opp-100000000 {
241          opp-hz = /bits/ 64 <100000000>;
242          required-opps = <&rpmhpd_opp_svs>;
243        };
244
245        opp-202000000 {
246          opp-hz = /bits/ 64 <202000000>;
247          required-opps = <&rpmhpd_opp_svs_l1>;
248        };
249      };
250    };
251